Double-side graph chip inverse single package structure and package method thereof

Abstract

The invention relates to a double-side graph chip inverse single package structure and a package method thereof. The structure comprises pins (2), unpacked molding compounds (epoxy resins) (3), tin bonding materials (6), a chip (7) and packed molding compounds (epoxy resins) (9), wherein the front sides of the pins (2) extend to be below a subsequent attached chip; the chip (7) is arranged on first metal layers (4) at the front sides of the pins (2) below the subsequent attached chip via the tin bonding materials (6); the packed molding compounds (9) are packaged above the pins (2) and outside the chip (7); and the unpacked molding compounds (3) are embedded in the peripheral areas of the pins (2) and in the areas between the pins (2). The package structure is characterized in that the packed molding compounds (9) cover the front local units of the pins (2); and columns (10) are arranged at the back of the pins (2) and the roots of the columns (10) are embedded in the unpacked moldingcompounds (3). The package structure can bear superhigh temperature during loading and can not undergo lead frame distorsion due to different physical properties of different substances and can avoidthe problem of pin falling.

Description

(1) Technical field [0001] The invention relates to a double-sided graphic chip flip-chip single package structure and a package method thereof. It belongs to the technical field of semiconductor packaging. (2) Background technology [0002] The traditional manufacturing method of the chip packaging structure is: after chemical etching and surface electroplating are carried out on the front side of the metal substrate, the production of the lead frame is completed (such as Figure 7 shown). The backside of the leadframe is etched during the packaging process. This law has the following shortcomings: [0003] Because only half-etching work is done on the front of the metal substrate before plastic sealing, and the plastic sealing material is only half a foot high to cover the pins during the plastic sealing process, so the binding ability between the plastic package and the pins becomes smaller. If the plastic package is considerate When the chip is not very good on the PC...

AI Technical Summary

Problems solved by technology

[0010] However, there are still following deficiencies: before encapsulation, the wrapping pin operation of the backside of the lead frame without filler molding compound is carried out, and when the high-temperature chip loading and wiring operations on the front of the lead frame are carried out, the lead frame and the filler-free plastic sealant The physical properties of the two materials are different, the expansion coefficients of the two materials are also different, and the heat deformation at high temperature is different, which leads to the distortion of the lead frame during subsequent chip mounting.

Therefore, this kind of packaging structure cannot withstand ultra-high temperature (above 200°C) when mounting chips

In the past, the requirement of high temperature resistance was achieved by making the package volume very large, but now the package volume is required to be smaller and the power is larger and larger, and it cannot withstand ultra-high temperature.

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