Method for analyzing masks for photolithography
Patent Information
- Authority / Receiving Office
- CN · China
- Current Assignee / Owner
- CARL ZEISS SMT GMBH
- Publication Date
- 2011-04-06
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Abstract
Description
technical field
[0001] The present invention relates to a method of analyzing reticles for lithography, wherein lithographic wafer exposure is simulated. Background technique
[0002] The development trend in the production of semiconductor structures, such as those used in processors in computer technology and now more often also in exchangeable storage media, is towards the production of smaller structures in the same area. Currently available computer chips consist of about 30 different layers stacked one on top of the other, and the size of the functional structures, so-called features, is about 45 nm. The photolithographic masks used to fabricate these features must be fabricated with correspondingly high precision. In this case, the wafer is exposed up to thirty times, and a different mask is required for each layer.
[0003] Aerial image analysis, for example by means of the AIMS of Carl Zeiss SMS GmbH, has long been known and established for the analysis and final ...