Method of forming integrated circuit structure

Abstract

A method of forming an integrated circuit structure includes providing a wafer having a silicon substrate; forming a plurality of shallow trench isolation (STI) regions in the silicon substrate; and forming recesses by removing top portions of the silicon substrate between opposite sidewalls of the plurality of STI regions. Substantially all long sides of all recesses in the silicon substrate extend in a same direction. A III-V compound semiconductor material is then epitaxially grown in the recesses.

Description

technical field [0001] The invention relates to a method for forming an integrated circuit structure, in particular to a III-V group semiconductor material with reduced defects. Background technique [0002] The speed of the metal oxide semiconductor transistor is closely related to the driving current of the metal oxide semiconductor transistor, and the driving current is further related to the charge mobility. For example, when the electron mobility in the channel region is high, the NMOS transistor has a high driving current, and when the hole mobility in the channel region is high, the PMOS transistor has a high driving current. Therefore, compound semiconductor materials of group III and group V elements (hereinafter referred to as group III-V compound semiconductor materials) can be excellent materials for forming NMOS devices due to their high electron mobility. [0003] The current problem is that it is difficult to fabricate thin layers of III-V compound semiconduc...

AI Technical Summary

Problems solved by technology

Although the III-V compound semiconductors formed by this method generally have lower defect densities than III-V compound semiconductors grown on blanket silicon wafers, they still have high defect densities.

Images