On-chip cache structure used for variable memory access mode of general-purpose stream processor
An on-chip cache and stream processor technology, applied in the cache structure field of stream processors, can solve problems such as the inability to change the ratio of cache and scratchpad memory at will, performance reduction, and poor structural flexibility, achieving low cost, meeting performance requirements, and realizing simple effect
Inactive Publication Date: 2012-08-22
NAT UNIV OF DEFENSE TECH
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Problems solved by technology
However, the configurable structure of Fermi has poor flexibility, and the ratio of cache and scratchpad memory cannot be changed at will, resulting in reduced performance when processing some special applications.
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[0018] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0019] Such as figure 1 As shown, the present invention is used for the on-chip cache structure of the variable memory access pattern of general-purpose stream processor, comprises storage array unit, cache controller, scratchpad memory controller and storage array boundary division logic unit, and storage array unit is formed by storage array The boundary division logical unit is divided into a cache part and a scratchpad memory part, the cache controller is used to access the cache part in the storage array unit, and the scratchpad memory controller is used to access the scratchpad memory part in the storage array unit. It can be seen that the on-chip cache of the present invention can support two access modes, each access mode has its own corresponding control structure, and the two access modes share one storage array. In this em...
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The invention discloses an on-chip cache structure used for a variable memory access mode of a general-purpose stream processor, which comprises a memory array unit, a cache controller, a scratch pad memory controller and a memory array boundary segmentation logical unit, wherein the memory array unit comprises a cache part and a scratch pad memory part which are segmented through the memory array boundary segmentation logical unit, the cache controller is used for accessing the cache part in the memory array unit, and the scratch pad memory controller is used for accessing the scratch pad memory part in the memory array unit. The on-chip cache structure has the advantages of simple and compact structure, low cost, good reliability and a wide range of applications, and can change the sizeratio of the cache to the scratch pad memory, meet the performances of the processor to the maximum extent and the like.
Description
technical field [0001] The invention mainly relates to the field of cache structure of stream processors, in particular to an on-chip cache structure suitable for variable memory access modes of general stream processors. Background technique [0002] In the latest high-performance microprocessor structure research, stream architecture is becoming a research hotspot, and a variety of processors with stream processing characteristics have emerged, such as the Imagine stream processor designed by Stanford and the STI (Sony, Toshiba, IBM) alliance The launched Cell processor and so on. Streaming architectures can effectively alleviate memory wall bottlenecks, exploit multiple levels of program parallelism, and have been shown to greatly improve processing performance for applications such as media processing and data-intensive scientific computing. Currently mainstream processors and graphics card manufacturers are researching and launching processors with stream processing fe...
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IPC IPC(8): G06F12/02
Inventor 邢座程付桂涛陈小保马安国黄平汤先拓何锐王庆林晏小波李方圆邱建雄蔡放闵银皮梅家祥孟晓冬赵齐王宏燕
Owner NAT UNIV OF DEFENSE TECH