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Rack-mount synchronous Ethernet architecture and clock synchronization control method

A technology of synchronous clock and synchronous clock source, which is applied in the field of Ethernet data communication to achieve reliable clock recovery, reduce equipment cost, and improve flexibility

Active Publication Date: 2011-05-04
武汉神州数码云科网络技术有限公司
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  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0006] The rack-type synchronous Ethernet architecture and the clock synchronization control method proposed by the present invention solve the problem of realizing reliable clock recovery, clock synchronization, and clock synchronization of each service board in the rack-type Ethernet switch device without using a special clock board. Technical Issues of Debounce and Delivery of Synchronized Timestamp

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  • Rack-mount synchronous Ethernet architecture and clock synchronization control method
  • Rack-mount synchronous Ethernet architecture and clock synchronization control method
  • Rack-mount synchronous Ethernet architecture and clock synchronization control method

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Embodiment Construction

[0036] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0037] The present invention aims to provide a rack-mounted synchronous Ethernet solution, and its specific implementation will be described in detail below.

[0038] The invention mainly proposes the M-LVDS solution for the backplane circuit of the synchronous Ethernet aiming at the rack-type switch. The topology of the above M-LVDS solution includes one or more synchronous recovered clock wiring topologies, one or more synchronous time stamp wiring topologies, and may also include one or more synchronous recovered clock event alarm information wiring topologies.

[0039] Such as figure 1 , as an embodiment of the synchronous Ethernet clock backplane topology, a plurality of differential signals CLK0 (main synchronous clock), CLK1 (standby synchronous clock), SIG0, SIG1, SIG2 driven by the M-LVDS driver 2 are introduced on the backplane , SIG3 (other...

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Abstract

The invention discloses a rack-mount synchronous Ethernet architecture and a clock synchronization control method. A back board topology structure is designed according to an M-LVDS (multiple low voltage differential signaling) scheme; each service board card selects a synchronous clock through a multiplexer, and a phase locked loop is used to process the synchronous clock, so that all service ports in the rack can serve as master ports of the synchronous Ethernet and also can serve as slave ports of the synchronous Ethernet. By using the rack-mount synchronous Ethernet architecture and the clock synchronization control method, a special block board card is eliminated for processing, and the equipment cost is reduced; and the flexibility of the clock source selection is improved, and reliable clock restoration, clock synchronization, clock degittering and the transmission of a synchronous time stamp are facilitated.

Description

technical field [0001] The invention relates to the field of Ethernet data communication, in particular to the implementation and architecture design of the synchronous Ethernet of rack-type data switches. Background technique [0002] In traditional Ethernet communication, clock synchronization is not required. Therefore, the design of traditional Ethernet switches, including rack switches and box switches, does not need to consider clock synchronization. However, with the development of Ethernet technology and the promotion of the integration of three networks in our country, there is more and more demand for synchronous Ethernet in the market. Various equipment manufacturers have also begun to seek support for synchronous Ethernet. [0003] In Ethernet communication, the most important ones are switching chips and physical layer (PHY) chips. Both chips need to support synchronous Ethernet technology to form a complete synchronous Ethernet. With the development of tech...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04J3/06H04L7/00
Inventor 邹泓
Owner 武汉神州数码云科网络技术有限公司
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