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Rack-mount synchronous Ethernet architecture and clock synchronization control method

A synchronous clock and Ethernet technology, applied in the field of Ethernet data communication, to achieve reliable clock recovery, improve flexibility, and reduce equipment costs

Active Publication Date: 2014-12-17
武汉神州数码云科网络技术有限公司
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  • Description
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AI Technical Summary

Problems solved by technology

[0006] The rack-type synchronous Ethernet architecture and the clock synchronization control method proposed by the present invention solve the problem of realizing reliable clock recovery, clock synchronization, and clock synchronization of each service board in the rack-type Ethernet switch device without using a special clock board. Technical Issues of Debounce and Delivery of Synchronized Timestamp

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  • Rack-mount synchronous Ethernet architecture and clock synchronization control method
  • Rack-mount synchronous Ethernet architecture and clock synchronization control method
  • Rack-mount synchronous Ethernet architecture and clock synchronization control method

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Embodiment Construction

[0036] The present invention will be further described below with reference to the drawings and embodiments.

[0037] The present invention aims to provide a solution for rack-mounted synchronous Ethernet, and its specific implementation will be described in detail below.

[0038] The present invention mainly proposes a M-LVDS solution of the backplane circuit of the synchronous Ethernet for the rack-mounted switch. The topology of the above-mentioned M-LVDS solution includes one or more synchronous recovery clock wiring topologies, one or more synchronous timestamp wiring topologies, and one or more synchronous recovery clock event alarm information wiring topologies.

[0039] Such as figure 1 As an embodiment of the synchronous Ethernet clock backplane topology, multiple differential signals CLK0 (main synchronous clock), CLK1 (standby synchronous clock), SIG0, SIG1, SIG2 driven by M-LVDS driver 2 are introduced on the backplane , SIG3 (other synchronous trigger signals), etc. Th...

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Abstract

The invention discloses a rack-mount synchronous Ethernet architecture and a clock synchronization control method. A back board topology structure is designed according to an M-LVDS (multiple low voltage differential signaling) scheme; each service board card selects a synchronous clock through a multiplexer, and a phase locked loop is used to process the synchronous clock, so that all service ports in the rack can serve as master ports of the synchronous Ethernet and also can serve as slave ports of the synchronous Ethernet. By using the rack-mount synchronous Ethernet architecture and the clock synchronization control method, a special block board card is eliminated for processing, and the equipment cost is reduced; and the flexibility of the clock source selection is improved, and reliable clock restoration, clock synchronization, clock degittering and the transmission of a synchronous time stamp are facilitated.

Description

Technical field [0001] The present invention relates to the field of Ethernet data communication, in particular to the implementation mode and architecture design of a synchronous Ethernet of a rack-mounted data switch. Background technique [0002] In traditional Ethernet communication, clock synchronization is not required. Therefore, the design of traditional Ethernet switches, including rack switches and box switches, does not need to consider clock synchronization. However, with the development of Ethernet technology and the advancement of my country's triple play, there is more and more demand for synchronous Ethernet in the market. Various equipment manufacturers have also begun to seek support for synchronous Ethernet. [0003] In Ethernet communication, the most important thing is the switch chip and the physical layer (PHY) chip. Both chips need to support synchronous Ethernet technology to form a complete synchronous Ethernet. With the development of technology, the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L7/00H04J3/06
Inventor 邹泓
Owner 武汉神州数码云科网络技术有限公司
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