Phase discriminator and phase locked loop circuit

Abstract

A phase discriminator and a phase-locked loop circuit are disclosed. The discriminator comprises a first clock input circuit used for receiving a first clock signal and generating a first comparison signal to be output according to the first clock signal, a second clock input circuit used for receiving a second clock signal and generating a second comparison signal to be output according to the second clock signal, a phase difference pulse output circuit connected with the output ends of the first clock input circuit and the second clock input circuit and used for generating a positive phase difference pulse signal to be output according to the first comparison signal and the second comparison signal. The phase discriminator and phase-locked loop circuit could reduce the workload of programming a microprocessor and reduce the burden of the microprocessor.

Description

technical field [0001] The invention relates to a phase detector and a phase-locked loop circuit, in particular to a one-way clock phase detector and a phase-locked loop circuit for realizing clock phase-locking in a synchronous communication system. Background technique [0002] Clock synchronization is a very important part in the communication network. A special digital synchronization network is set up in the communication network of our country. The digital synchronization network is the support network of the communication network and is used to provide synchronous clock signals for the communication network. In order to ensure the normal operation of the communication network, a digital synchronization network is usually used to keep the clock frequency and phase of all nodes in the communication network consistent. The level of my country's digital synchronization network system is master-slave synchronization, and the lower-level nodes obtain the frequency reference...

AI Technical Summary

Problems solved by technology

However, when the phase detector detects the phase of the clock signal, because the frequency of the measured signal always changes slowly, especially in a loosely coupled phase-locked loop, the phase of the measured signal may be ahead of the reference signal at a certain moment, and a certain The measured signal will lag behind the reference signal at a moment, so the obtained phase detection result will be positive or negative

Since the phase detection results of the phase detector need to be output to the loop filter for processing, and the loop filter is implemented by a microprocessor, both positive and negative phase detection results will increase the burden on the processor

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