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Systematized RISC CPU (Reduced Instruction-Set Computer Central Processing unit) production line control method

A RISCCPU and control method technology, applied in machine execution devices, concurrent instruction execution, etc., can solve problems such as increasing the difficulty of pipeline control logic circuits

Inactive Publication Date: 2013-08-07
SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the depth of the pipeline increases, during the execution of instructions, the situation of empty state (NOP) or pipeline hazard (HAZARD) in each pipeline will become more complicated, which greatly increases the difficulty of pipeline control logic circuit design.

Method used

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  • Systematized RISC CPU (Reduced Instruction-Set Computer Central Processing unit) production line control method
  • Systematized RISC CPU (Reduced Instruction-Set Computer Central Processing unit) production line control method
  • Systematized RISC CPU (Reduced Instruction-Set Computer Central Processing unit) production line control method

Examples

Experimental program
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Effect test

Embodiment 1

[0027] Such as image 3 As shown, the schematic diagram of the pipeline execution for the F-level exception can be seen: when the instruction cache does not hit, the instruction fetch operation fails, that is, there is no instruction in this cycle, and the F-level inserts a bubble, but the D-level pipeline will not be executed in the next clock cycle; just The pipeline enable signal E 1 Set to 0, N 1 Set to 1 (empty state).

Embodiment 2

[0029] Such as Figure 4 As shown, the schematic diagram of the pipeline execution for D-level exceptions can be seen: since the register bank has only three read ports, when the instruction needs to read four registers, the pipeline stalls; only need to turn the pipeline self-locking signal L 1 set to 1.

Embodiment 3

[0031] Such as Figure 5 As shown, the schematic diagram of pipeline execution for E-level multi-cycle execution exception can be seen: when the instruction is multi-cycle execution end instruction such as multiplication, the front-stage pipeline will be stopped, and the subsequent-stage pipeline will start to execute in the last cycle, and the multiplication instruction will be in the pipeline E Level implementation requires 1 to 5 clock cycles. When it is not the last clock cycle, the enable signal E 3 Set to 0, self-locking signal L 3 Set to 1, otherwise solve according to the recursive formula;

[0032] Another example Figure 6 As shown, the schematic diagram of pipeline execution for E-level branch and jump exceptions can be seen: when the instruction is a branch or jump instruction, the instruction before the instruction runs normally, but the execution instruction after the instruction is an error instruction, that is, F, D The command being executed. Pipeline con...

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Abstract

The invention discloses an RISC CPU (Reduced Instruction-Set Computer Central Processing unit) production line control method. Pausing factors of a production line at each level are systematically analyzed, whether the distributor data of the production line at the current stage are refreshed or not is determined by two factors: whether an instruction needs to refresh a register and whether the operation is stopped by a later-level executed instruction, i.e. the production line is paused; in addition, a recursion formula for logic control is proposed. The logic control of the production lineprovided by the invention is systematized, the execution flow control on every kind of instructions is only independently considered, namely, whether next-level production line is needed executing bythe instruction and whether the former-level production line is needed pausing by the instruction, but the relation between every two instructions is not needed to be considered, thus the design on system instructions is simplified and a deeper production line can be expanded.

Description

technical field [0001] The invention relates to a pipeline logic control method in a RISC CPU. The method systematically proposes the conditions for refreshing registers of each pipeline level and the recursive publicity of control signals, and is suitable for pipelines with similar circuit structures and arbitrary high depths. control. Background technique [0002] With the development of integrated circuit technology, a large number of embedded 32-bit RISC CPU microprocessors are popular in the market. In recent years, the country has vigorously supported the research and development of general-purpose and special-purpose microprocessors with independent intellectual property rights through the 863 VLSI major project of the Ministry of Science and Technology, and has achieved remarkable results. RISC (Reduced Instruction Set Computer) is a microprocessor that executes fewer types of computer instructions. The pipeline and common instructions are implemented by hardware, a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38
Inventor 章其富张耀辉
Owner SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI
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