MTP (multi-time programmable) device unit structure and operating method thereof

Abstract

The invention discloses an MTP device unit structure. A programmable terminal (WL) is arranged on one side of a selective transistor, a drain terminal (BL) is arranged on one side of a programmable transistor (20), and a series resistor is arranged at the programmable terminal (WL) or the drain terminal (BL). The invention also discloses an operating method of the MTP device unit structure. The MTP device unit structure provided by the invention is suitable for the programmable transistor with a thick gate oxide layer, and can improve programming speed and programming efficiency.

Description

technical field [0001] The present invention relates to an NVM (Non Volatile Memory, non-volatile memory), in particular to an MTP (Multi-Time Programmable, multi-programmable) NVM device. Background technique [0002] Chinese invention patent application publication CN101373634A (published on February 25, 2009) discloses a MTP device unit structure, which can be manufactured by common CMOS logic process without adding any additional mask or process steps. [0003] see Figure 1a , a conventional MTP cell structure disclosed in the above patent application includes a selection transistor 10 , a programming transistor 20 and an erasing transistor 30 . The source 11 of the selection transistor 10 is used as the drain BL, the gate 12 of the selection transistor 10 is used as the selection terminal SG, and the drain 13 of the selection transistor 10 is connected to the source 21 of the programming transistor 20 . The gate of the program transistor 20 and the gate of the erase t...

AI Technical Summary

Problems solved by technology

[0010] Second, when the above-mentioned MTP device unit structure is programmed, the holes generated by the impact ionization in the channel of the programming transistor 20 need to drift 2 channel regions (that is, the channel region of the programming transistor 20 and the channel region of the selection transistor 10) , can be absorbed by the negative power supply drain terminal BL, which greatly affects the programming speed of MTP devices

[0011] Third, see image 3 , due to the above two deficiencies, when the thickness of the gate oxide layer of the programming transistor 20 (i.e. the silicon dioxide below the floating gate 22, sometimes also referred to as the tunnel oxide layer) is greater than Tox2, the performance of the gate oxide layer The degree of band bending is small, the distance between the top of the valence band Ev in the channel region and the top of the conduction band Ec of the gate oxide layer is large, and the electrons generated after the holes are impacted and ionized in the channel need to overcome a large potential barrier to cross the gate oxide layer. layer, which requires greater energy or longer time, manifested as less efficient programming

[0012] see Figure 4 , the test found that the above-mentioned MTP device unit structure, when the drain terminal BL is connected to a voltage of 2.5V, the programming terminal WL is connected to a voltage of 3.5V, the selection terminal SG is connected to a voltage of 0V, and the erasing terminal EG is connected to a voltage of 0-3.5V, When the thickness of the gate oxide layer of the programming transistor 20 is When the programming voltage is 9V, it takes up to 1s to complete the programming ( Figure 4 middle square), the programming speed is very slow, and the programming efficiency is too poor

Therefore, the existing MTP device unit structure can only be applied to the case where the thickness of the gate oxide layer of the programming transistor 20 is relatively thin ( ), which cannot be applied to the thicker gate oxide layer of the programming transistor 20 ( above)

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