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Method for cleaning technological cavities of semiconductor

A process cavity and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as shortening the life of electrostatic chucks and affecting tool productivity

Active Publication Date: 2011-07-27
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, increased WAC time and intensity will shorten the life of the electrostatic chuck
Another prior art solution is to increase the frequency of maintenance, but this affects tool productivity

Method used

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  • Method for cleaning technological cavities of semiconductor
  • Method for cleaning technological cavities of semiconductor
  • Method for cleaning technological cavities of semiconductor

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Experimental program
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Embodiment Construction

[0028] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0029] Table 2 is a schematic diagram of process parameters of a cleaning method for a process chamber (for example, an etching chamber) according to a preferred embodiment of the present invention.

[0030] The WAC process parameter table of table 2 preferred embodiment

[0031]

[0032] The cleaning method shown in Table 2 is suitable for cleaning the etching chamber of semiconductor devices using ultra-low-k dielectric layers, and is roughly divided into two stages, namely, the WAC stage and the argon (Ar) flushing stage.

[0033] The WAC stage consists ...

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PUM

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Abstract

The invention provides a method for cleaning technological cavities of a semiconductor. The technological cavities are provided with limiting rings for limiting the cleaning and blowing positions of the scavenge gases. The method comprises the steps: a) carrying out a plurality of continuous waferless auto clean procedures and b) cleaning and blowing argon in the technological cavities, wherein the positions of the limiting rings are changed and the scavenge gases are cleared and blown in each procedure. By adopting the method, the residual particles in the cavities can be effectively removedto maintain the residual particles at a lower acceptable level. The method has the beneficial effects of dispensing with additional cost which is needed in the traditional scheme in which the hardware is changed and having no negative effect on the productivity due to no change of the procedures.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a wafer-free automatic cleaning process cleaning process. Background technique [0002] The development of semiconductor integrated circuit technology has put forward new requirements for interconnection technology, and interconnection integration technology will face a series of technical and physical constraints in the short-term and long-term development. As the dimensions of semiconductor devices continue to shrink, interconnect structures become narrower, resulting in higher and higher interconnect resistances. With its excellent conductivity, copper has become one of the solutions for interconnection integration technology in the field of integrated circuit technology. Copper interconnection technology has been widely used in the technology of 90nm and 65nm technology nodes. [0003] In the copper interconnection process, since the space between the metal lines is g...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/00
Inventor 孙武张海洋黄怡
Owner SEMICON MFG INT (SHANGHAI) CORP
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