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Method for extracting charge distribution of metal oxide semiconductor (MOS) tube along channel

A technology of MOS tube and charge distribution, which is applied to circuits, measurement electronics, electrical components, etc., can solve problems such as cumbersome process and complicated calculation process

Active Publication Date: 2011-08-24
SEMICON MFG INT (BEIJING) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Since most of the traditional charge pump methods can only calculate the average charge density generated at the entire interface, although someone can roughly calculate the distribution of the interface state and dielectric layer charges along the channel direction due to stress by changing the test conditions and structure, However, a very complicated calculation process is required. It is necessary to continuously change the gate pulse amplitude or change the bias voltage between the drain and the substrate to measure a series of charge pump curves under different gate pulse reference voltages. According to the obtained maximum current Obtain the distribution of each new charge along the channel direction
Therefore, the traditional charge-pump-based method to extract the interface state of the device along the channel direction and the charge distribution of the gate dielectric layer requires a large number of tests and calculations, and the process is quite cumbersome.

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  • Method for extracting charge distribution of metal oxide semiconductor (MOS) tube along channel

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Embodiment Construction

[0046] The preferred embodiments of the present invention will be described in more detail below with reference to the drawings.

[0047] The MOS tube tested in this embodiment is an NMOS (PMOS is similar), and an NMOS tube with good process conditions and uniform interface states is selected, and the width (W) and length (L) are 6um and 0.5um, respectively. After 1000s of hot carrier stress injection, the interface state and the charge of the gate dielectric layer were tested. Such as figure 1 A charge pump current test method with an open circuit at one end of the source and drain and a section of reverse bias voltage is used. Add a fixed frequency and fixed amplitude pulse voltage to the grid, the amplitude of the pulse voltage should be greater than the threshold voltage V th Flat belt voltage V fb Scan the reference voltage at the same time, so that two sets of charge pump current curves before and after stress can be obtained, see Figure 5 , Where the two origin curves c...

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Abstract

The invention discloses a method for extracting a charge distribution of metal oxide semiconductor (MOS) tube along a channel. The method is applied to extraction of the charge distribution of an interface state and a grid medium in the MOS tube. The method comprises the following steps of: adding the MOS tube into a test circuit, and testing two charge pump current curves with an open circuit at the drain end or the source end of the MOS tube before and after a stress by using a charge pump current test method, wherein one of the two charge pump current curves is an original curve and the other one is an after-stress curve; searching any point A on the original curve and a corresponding point B on the after-stress curve, and estimating a partially generated interface state charge and a grid medium charge quantity according to the charge pump current variable quantity of a partial point and the change of voltage. Compared with the conventional distribution extraction method, the method has the advantages of simply and quickly extracting the charge distribution from the drain or source end to the channel with the help of a computer, saving a large amount of complicated repeated tests and providing effective basis for reliability improvement of devices.

Description

Technical field [0001] The invention relates to the field of semiconductor device testing, in particular to a test extraction method for the interface state and gate dielectric charge distribution in a MOS tube. Background technique [0002] In recent decades, with the improvement of circuit integration, the device size has gradually shrunk to the deep sub-micron or even nanometer level. At the same time, as the feature size of the device shrinks, the device performance is constantly changing and developing. However, the reduction of device feature size also brings various reliability problems, which mainly include hot carrier effect, NBTI, and oxide layer breakdown over time (TDDB). The reliability problem is mainly due to the external stress caused Si / SiO in the device 2 Some traps are generated in the interface and the gate dielectric layer, which seriously affect various characteristics of small-sized devices. Therefore, the ability to accurately measure the interface state...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66G01R31/26G06F17/50
CPCG01R31/2621H01L22/14
Inventor 杨东谭斐安霞黄如张兴
Owner SEMICON MFG INT (BEIJING) CORP