A kind of FPGA-based at96 bus controller ip core and its construction method

A bus controller and construction method technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problems of low application efficiency, cumbersome configuration operations, poor portability, etc., to reduce application costs, simple configuration operations, and reduce CPU The effect of the load

Inactive Publication Date: 2014-10-29
BEIHANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But the disadvantages are high cost, poor portability, cumbersome configuration operations, and low application efficiency

Method used

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  • A kind of FPGA-based at96 bus controller ip core and its construction method
  • A kind of FPGA-based at96 bus controller ip core and its construction method
  • A kind of FPGA-based at96 bus controller ip core and its construction method

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Embodiment

[0048] figure 2 Shown is a block diagram of the functional module structure of the AT96 bus controller IP core based on FPGA. An embodiment of the present invention is described by taking a bus read and write access through the AT96 bus controller as an example.

[0049] 1, a kind of AT96 bus controller IP core based on FPGA of the present invention, as figure 2 As shown, it is composed of AT96 bus interface module (001), AT96 bus controller state machine module (002), FIFO cache module (003), local bus control module (004), local bus interface module (005) and functional configuration Module (006) consists of, such as figure 2 As shown, the position connection relationship and signal flow among them are as follows. a) One end of the AT96 bus interface module (001) is connected to the AT96 bus interface card, and the other end is connected to the AT96 bus controller state machine module (002), which receives data and control signals from the AT96 bus or sends data and contr...

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Abstract

The invention relates to an AT96 bus controller IP (internet protocol) core based on an FPGA (field programmable gate array), which comprises an AT96 bus interface module, an AT96 bus controller state machine module, a FIFO (first in, first out) cache module, a local bus control module, a local bus interface module and a function configuration module, wherein one end of the AT96 bus interface module is connected to an AT96 bus interface card while the other end is connected to the AT96 bus controller state machine module; the AT96 bus controller state machine module is connected to the FIFO cache module; the FIFO cache module is connected to the local bus control module; the local bus control module is connected to the local bus interface module; and the function configuration module is connected to later four modules. A construction method for the AT96 bus controller IP core based on FPGA comprises the following six steps: 1) design input; 2) function simulation; 3) logic composition; 4) pre-simulation; 5) a table file output; and 6) an IP core calling module output.

Description

1. Technical field [0001] The invention relates to the application of interconnection of communication single boards through the AT96 bus interface, in particular to an FPGA-based AT96 bus controller IP core and a construction method thereof, belonging to the technical field of communication equipment design and application. 2. Background technology [0002] In order to apply AT96 bus PCs in harsh industrial environments, the German SIEMENS company initiated the formulation of the AT96 bus European card standard (IEEE996) in 1994, and it has been popularized and applied in Europe. AT96 bus = AT96 bus electrical specification + 96-core pinhole connector + Eurocard specification (IEC297 / IEEE 1011.1). The AT96 bus industrial computer eliminates the golden finger connection between the templates, and has the ability to resist strong vibration and impact; its 16-bit data bus, 24-bit addressing capability, high reliability and good maintainability are more suitable for use in hars...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/20G06F13/24
Inventor 陈娟祁晓野马俊功王德义付永领
Owner BEIHANG UNIV
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