Wafer level package method

Abstract

The invention discloses a wafer level package method. A semiconductor component and an encapsulation substrate are combined tightly by using a secondary encapsulation manufacture procedure, so gaps between the wafer and the encapsulation substrate can be reduced, and the combining degree between the wafer and the encapsulation substrate can be improved.

Description

technical field [0001] The invention relates to a packaging method, in particular to a wafer-level packaging method. Background technique [0002] With the increasing demand for semiconductor light-emitting components, the demand for packaging capacity is also increasing. Therefore, many technologies have been revealed to increase the packaging capacity and production efficiency of semiconductor light emitting components, such as wafer level packaging (wafer level package, WLP) technology combined with micro-electromechanical system (micro-electromechanical system, MEMS), using yellow light (photolithography process) and lithography technology (lithography) complete the circuit design and wafer dicing at the wafer level to improve production efficiency and mass production. At the same time, it can also reduce the size of the packaging structure, which is a technology that meets modern needs. [0003] However, there are still many problems to be improved in the wafer-level p...

AI Technical Summary

Problems solved by technology

This prior art utilizes capillary phenomenon to allow the encapsulant to penetrate into the space between the die and the package substrate, but there will still be a gap between the die and the package substrate, which will cause the component package to be incomplete and affect the long-term reliability function

Images