High-speed data cache and collection system based on PCI (Peripheral Component Interconnect) bus

Abstract

The invention is applicable to the technical field of high-speed data cache and provides a high-speed data cache and collection system based on a PCI (Peripheral Component Interconnect) bus, which comprises a programmable logical unit, an FIFO (First in First out) unit and a PCI (Peripheral Component Interconnect) bus control chip. A group or a plurality of groups of received data is processed into have a data format matched with a current working mode by the programmable logical unit; the FIFO unit caches the data processed by the programmable logical unit through completely using cache resources under corresponding input-output bus width modes; and the PCI bus control chip controls the input-output bus width modes of the FIFO unit under the current working mode, controls a multi-path data combination control unit capable of controlling the data processing modes of the programmable logical unit, and is used for reading the cache data in the FIFO unit. Under the current working mode, the system processes the data into have the data format matched with the input-output bus width modes of the backward stage FIFO unit, thus reducing the requirements of the system architecture on the backward stage design and improving the flexibility and reliability of data transmission.

Description

technical field [0001] The invention belongs to the technical field of high-speed data cache, in particular to a PCI bus-based high-speed data cache and acquisition system. Background technique [0002] The design of the high-speed data cache and transmission system is the core of the high-speed PCI (Peripheral Component Interconnect, peripheral component interconnection standard interface) data transmission sequential logic system of the data acquisition card, and its realized functions include basic cache functions and transmission functions. [0003] The advantages and disadvantages of the cache and transmission architecture design adopted by the high-speed data cache and transmission system not only limit the upper limit of the data transmission rate of the high-speed PCI acquisition card and the flexibility of product function configuration, but also determine its development difficulty and cost. [0004] In the high-speed data acquisition system in the prior art, each ...

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Problems solved by technology

[0006] The purpose of the embodiment of the present invention is to provide a high-speed data cache and acquisition system based on the PCI bus, aiming at improving the problems of poor flexibility and reliability of system data transmission and bottlenecks in the upper limit of speed transmission in the prior art

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