Method for extracting and verifying latter interconnection delay model

Abstract

The invention provides a method for extracting and verifying a latter interconnection delay model. The method comprises the steps of: designing a discrete interconnection testing structure and a circuit level interconnection testing structure according to the process information of an integrated circuit; carrying out an interconnection delay parameter test; extracting the three-dimensional model parameters of the discrete interconnection testing structure by using a three-dimensional parasitic parameter extracting software, and calibrating the extracting results of the wafer testing result three-dimensional parameter extracting software; calibrating a simulation result of the three-dimensional parameter extracting software through the extracting result of a quasi-three-dimensional parameter extracting software; and finally, extracting the parameters of the whole circuit layout by using the quasi-three-dimensional parameter extracting software so that the precision of the extracted parameters can be compatible with the calculating speed of the parameters. The invention integrates the advantages of high precision of the three-dimensional parameter extracting software and higher calculation speed and fewer resource consumption of the quasi-three-dimensional parameter extracting software.

Description

technical field [0001] The invention relates to the technical field of integrated circuit technology, in particular to a method for extracting and verifying a back-channel interconnection delay model. Background technique [0002] With the development of integrated circuit technology, the operating frequency of the circuit is getting higher and higher, the feature size of the integrated circuit is continuously reduced, the device delay is also reduced, and the interconnection resistance is increased, the lateral capacitance of the interconnection layer and the edge As the capacitance increases, the delay of the interconnect line starts to play a major role, and the interconnect capacitance determines the total gate load. The data show that under the condition of 0.25μm process and 5-6 layer wiring technology, the interconnection delay accounts for about 60% of the total delay, so the interconnection parasitic effect in the circuit is more and more important to the impact of ...

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Problems solved by technology

[0007] Obviously, using a real 3D model and calculating the capacitance is the most direct way to achieve higher accuracy, but for a complex 3D str

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