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Method for filling redundant metal in manufacturing process of integrated circuit and semiconductor device

A redundant metal and manufacturing process technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of interference, noise energy, consumption, etc., and achieve the reduction of capacitance to ground. Small coupling capacitance, effect of reducing influence

Active Publication Date: 2014-02-12
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, redundant metal filling increases the coupling capacitance between the redundant metal and the circuit, which also brings a series of negative effects on circuit performance, such as signal delay, interference noise and energy consumption

Method used

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  • Method for filling redundant metal in manufacturing process of integrated circuit and semiconductor device
  • Method for filling redundant metal in manufacturing process of integrated circuit and semiconductor device
  • Method for filling redundant metal in manufacturing process of integrated circuit and semiconductor device

Examples

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Effect test

Embodiment 1

[0032] The method for filling redundant metal in the integrated circuit manufacturing process provided by the embodiment of the present invention aims to reduce the influence of coupling capacitance caused by redundant metal, see figure 1 , the method includes the steps of:

[0033] S1. Form interconnection trenches and redundant metal trenches respectively on the semiconductor substrate including the dielectric layer, and the depth of the redundant metal trenches is smaller than the depth of the interconnection trenches.

[0034] A semiconductor substrate is provided, and the semiconductor substrate can be a single crystal silicon or a polycrystalline silicon substrate, on which a dielectric layer, namely an oxide layer or an insulating layer is formed. The steps of forming interconnection trenches and forming redundant metal trenches on the dielectric layer are performed separately, and can be realized by processes such as photolithography and etching. see figure 2 , is a...

Embodiment 2

[0039] Embodiment 2 of the present invention is based on Embodiment 1. In Step S1 described in Embodiment 1, interconnect trenches and redundant metal trenches are respectively formed on the semiconductor substrate including the dielectric layer. The redundant metal trenches The depth is less than the depth of the interconnection groove, specifically in this embodiment:

[0040] S21 , forming interconnection line grooves according to the interconnection line pattern on the semiconductor substrate including the dielectric layer.

[0041] Further, see image 3 , the step S21, forming interconnection grooves according to the interconnection pattern on the semiconductor substrate including the dielectric layer, including:

[0042] S211. Deposit a barrier layer 2 on the semiconductor substrate including the dielectric layer 1, planarize the barrier layer 2 to coat the first photoresist layer 3, and transfer the interconnect pattern to the first photoresist layer 3. Form an openin...

Embodiment 3

[0064] see Figure 10 , Embodiment 3 of the present invention provides a semiconductor device aimed at reducing the impact of the coupling capacitance of interconnection lines due to the filling of redundant metal. The semiconductor device includes a multilayer interconnection structure 1, and interconnection structures of different layers The interconnection structure 1 of each layer includes a dielectric layer 3 and an interconnection metal 4 and a redundant metal 5 formed on the dielectric layer, wherein the redundant metal 5 thickness is less than the interconnect metal 4 thickness.

[0065] In the semiconductor device described in the embodiment of the present invention, the thickness of the redundant metal is smaller than the thickness of the metal of the interconnection line, so the distance between the redundant metal and the ground is reduced, and the capacitance to ground caused by the redundant metal is significantly smaller than that of the traditional method, and ...

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Abstract

The invention discloses a method for filling redundant metal in a manufacturing process of an integrated circuit, and relates to the technical field of semiconductor devices. By the adaption of method, influences of coupling capacitance caused by the redundant metal filling can be reduced. The method comprises the following steps of: forming an interconnection line trench and a redundant metal trench respectively on a semiconductor substrate comprising a medium layer, wherein the depth of the redundant metal trench is less than that of the interconnection line trench; and electroplating the interconnection line trench and the redundant metal trench, and carrying out planarization treatment on electroplated surface so as to form redundant metal with the thickness less than that of the interconnection line metal. The invention also discloses a semiconductor device which comprises a plurality of layers of interconnection structures, wherein each layer of interconnection structure comprises a medium layer, and the interconnection line metal and redudant metal which are manufactured on the medium layer, wherein the thickness of the redundant metal is less than that of the interconnection line metal. The method and the device provided by the invention are used for manufacturing an integrated circuit.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a method for filling redundant metal in the integrated circuit manufacturing process and a semiconductor device. Background technique [0002] Generally speaking, the fabrication of integrated circuits involves a series of layering processes in which metals, electrolytes, and other materials are applied to semiconductor substrates to form layered interconnect structures that pass through Vias connect the various layers of integrated circuits, making integrated circuits have high complexity and circuit density. [0003] When the feature size of integrated circuits (Integrated Circuit, IC) drops below 90 nanometers, in order to avoid reducing the yield rate in the multi-layer manufacturing process, in the manufacture of each layer, the circuit surface has better flatness is very important. If the flatness of the surface of the circuit layer is not good enough, it wi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/321H01L23/522
Inventor 周隽雄陈岚阮文彪李志刚王强叶甜春
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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