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Clock integrated circuit

A technology of integrated circuits and sequential circuits, applied in the direction of electrical components, electric pulse generation, pulse generation, etc., can solve the problems of consumption, large layout area, etc.

Active Publication Date: 2012-01-11
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such a circuit consumes a large amount of layout area and current

Method used

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  • Clock integrated circuit
  • Clock integrated circuit
  • Clock integrated circuit

Examples

Experimental program
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Embodiment Construction

[0112] figure 1 A block schematic diagram of an integrated circuit clock circuit with tolerance to variations such as temperature, ground voltage, or supply voltage is shown.

[0113]The integrated circuit clock circuit is usually a one-loop structure with a timing circuit 102 , a level switching circuit 104 and a latch circuit 106 . The latch circuit 106 generates a feedback signal from the latch circuit 106 to the sequential circuit 102 and a clock output signal 110 . The timing circuit 102 switches between the two reference signals according to a time constant. This time constant thus determines the timing of the integrated circuit clock circuit. A typical example of a time constant is an exponential time constant, which characterizes the rise and fall times of an RC circuit or RL circuit. The level switching circuit monitors the output of the timing circuit 102 and changes its output according to whether the timing circuit 102 is high or low enough. Examples of the lat...

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Abstract

The invention discloses a clock circuit of an integrated circuit. The clock circuit can operate under the bearing of power variation. A supply voltage supplies power to a compensation circuit; the compensation circuit generates a compensation reference voltage; the compensation reference voltage compensates the variation of the supply voltage; and a comparison circuit compares an output of a time sequence circuit with the compensation reference voltage to determine the time sequence of a clock signal.

Description

technical field [0001] The present invention relates to integrated circuits with clock circuits that are tolerant to variations such as temperature, ground noise, power supply noise, and the like. Background technique [0002] The operation of the clock circuit of an integrated circuit will vary with factors such as temperature, ground noise, and power supply noise. Since these variations will affect the final timing of the output clock signal, a number of studies have been conducted to address this issue and produce a more uniform output clock signal in the presence of the above variations. [0003] For example, US Pat. No. 7,142,005 to Gaboury uses a buffer circuit with an active load, independent bias circuitry, and bias circuitry to isolate the clock signal from power fluctuations. In order to isolate the impact of power supply fluctuations on the clock signal, these relatively complex buffer circuits cause a significant increase in die area and cost. [0004] In anoth...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/012
Inventor 陈重光
Owner MACRONIX INT CO LTD