Phase adjustment circuit

Abstract

In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first ½ frequency division circuit having a phase inversion function generates an intermediate reference clock apart in phase from both a phase reference clock and a phase-adjusted clock. A first phase control circuit controls the phase of the intermediate reference clock to be in a desired phase state with respect to the phase reference clock. A second phase control circuit controls the phase of the phase-adjusted clock to be in a desired phase state with respect to the intermediate reference clock. Thus, when the phase-adjusted clock is adjusted to be close in phase to the phase reference clock, the phase difference between these clocks can be determined correctly and stably even if it varies due to clock jitter.

Description

technical field [0001] The present invention relates to an improvement of a phase adjustment circuit that generates and outputs a phase-adjusted clock having a predetermined phase difference with respect to a phase-reference clock when an input clock or the like is used as a reference clock for phase adjustment. Background technique [0002] Generally, when generating a clock with a duty ratio (Duty) of 50%, the following method is known as the simplest method: generate a frequency-multiplied clock that requires a clock frequency with a duty ratio of 50%, and use a divide-by-two circuit to generate the clock frequency. The clock is divided to generate a clock with a 50% duty cycle. [0003] However, the phase state of the output clock of the divide-by-2 circuit depends on the initial state of the divide-by-2 circuit, and there are two states different in phase from each other by 180°. Therefore, when the method is applied to a phase adjustment circuit that generates a phase...

AI Technical Summary

Problems solved by technology

[0017] However, in a phase adjustment circuit that generates a phase adjustment clock with a duty ratio of 50% in the prior art, there is a problem that when the phase adjustment clock is adjusted to a phase close to that of the phase reference clock, the higher the clock frequency, or the higher the phase resolution The higher the value, the smaller the phase difference between the phase reference clock and the phase adjustment clock. Therefore, if the phase difference changes due to clock jitter, the determination of the phase relationship between the phase reference clock and the phase adjustment clock in the phase control circuit will be unstable. The phase inversion action of the phase adjustment clock will be repeated

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