Electrostatic protection circuit of submicron integrated circuit

An integrated circuit, electrostatic protection technology, used in circuits, electrical components, electrical solid devices, etc.

Active Publication Date: 2012-02-01
WUXI CRYSTAL SOURCE MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006]Technical problem: the purpose of the present invention is to provide an effective electrostatic discharge electrostatic protection circuit for submicron integrated circuits, which solves the problem of uneven conduction in the conventional GGNMOS structure The problem and the problem that the coupling capacitance in the GCNMOS structure affects the input and output signals provide better ESD protection for sub-micron integrated circuits without adding additional process steps, so as to improve the ESD protection ability of integrated circuits without using The process is complicated, avoiding the increase of cost and improving the competitiveness of products

Method used

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  • Electrostatic protection circuit of submicron integrated circuit
  • Electrostatic protection circuit of submicron integrated circuit
  • Electrostatic protection circuit of submicron integrated circuit

Examples

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Effect test

Embodiment Construction

[0016] A submicron integrated circuit electrostatic protection circuit, used for ESD protection of internal circuits, such as Figure 4 shown, including:

[0017] NMOS tube (M3) is an ESD discharge tube, the drain of M3 is connected to the internal PIN of the protected circuit, the source and substrate of M3 are short-circuited to GND, and C2 is the parasitic capacitance between the gate and drain of M3 , the gate of M3 is connected to the drain of the NMOS transistor (M4);

[0018] The drain of M4 is connected to the gate of M3, the source of M4 is shorted to the substrate and connected to GND, and the gate of M4 is connected to the negative terminal of R2 and the positive terminal of C3;

[0019] The positive terminal of R2 is connected to the power supply VCC, the negative terminal of R2 is connected to the gate of M4, and the resistance of R2 is 10~20KΩ;

[0020] The positive terminal of C3 is connected to the gate of M4, the negative terminal of C3 is connected to GND, ...

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Abstract

The invention discloses an electrostatic protection circuit of a submicron integrated circuit, comprising a first NMOS (N-metal-oxide-semiconductor) tube, a second capacitor, a second NMOS tube, a second resistor, a third capacitor and a first diode. The electrostatic protection circuit is used for solving the problems that the conduction is uneven and the coupling capacitance influences input and output signals in a GCNMOS (grounded-gate negative-channel metal oxide semiconductor) structure and provides preferable ESD (electrostatic discharge) protection for the submicron integrated circuit as well as is in no need of additional processing steps, thus reaching the purposes of improving the ESD electrostatic protection capacity of the integrated circuit and simplifying the technology, avoiding the cost increment and improving the product competitiveness.

Description

technical field [0001] The invention relates to an ESD protection circuit providing effective electrostatic protection for submicron integrated circuits, which belongs to the technical field of semiconductor manufacturing. Background technique [0002] ESD (Electrostatic Discharge) is one of the most important reliability issues for integrated circuits today. With the development of integrated circuit manufacturing technology and the continuous reduction of feature size, the antistatic ability is getting weaker and weaker. According to statistics, more than 1 / 3 of the failure of integrated circuits is caused by ESD. In order to reduce the adverse effects of ESD on integrated circuits and improve the reliability of integrated circuits, the most effective way is to add various ESD protection circuits to integrated circuits. [0003] In the conventional CMOS process, the GGNMOS (Gate Grounded NMOS) structure is generally used to provide effective ESD protection for the circuit...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02
Inventor 朱伟民马晓辉聂卫东
Owner WUXI CRYSTAL SOURCE MICROELECTRONICS CO LTD
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