Light-emitting diode assembly and packaging method thereof
A technology for light-emitting diodes and packaging methods, which is applied to electrical components, electrical solid-state devices, semiconductor devices, etc., can solve the limitations of increasing the processing and manufacturing cost of light-emitting diode components, the size of high-power light-emitting diode components, photoelectric conversion efficiency and heat dissipation efficiency, The power performance of the LED module is not as good as expected, etc.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0026] Such as figure 1 The flow chart of the packaging of light-emitting diode components of the present invention, figure 2 The top view of the structure of the light emitting diode assembly according to Embodiment 1 of the present invention, image 3 As shown in the cross-sectional view of the light emitting diode assembly structure of Embodiment 1 of the present invention, the packaging method of the light emitting diode assembly of the present invention includes the following steps:
[0027] a. Provide a carrier 10, the carrier 10 has a metal substrate 11, an insulating layer 12 and a copper foil layer 13 are successively provided on the plate surface of the metal substrate 11; the copper foil layer 13 is separated by at least two blocks 131 , the copper foil layer 13 and at least one external power contact 132 are respectively formed on two predetermined blocks 131 .
[0028] b. With at least one chip 21 as a light emitting unit 20, a predetermined number of chips 21 ...
Embodiment 2
[0037] The difference between this embodiment and Embodiment 1 is that each light emitting unit 20 is as Figure 4 As shown, at least one chip 21 of upper and lower electrode type (upper in the figure) and at least one chip 21 of planar electrode type (lower in the figure) are included, so that each light emitting unit 20 has better color rendering.
Embodiment 3
[0039] The difference between this embodiment and Embodiment 1 or 2 is that the chip 21 in the present invention is relatively deep into the predetermined depth under the carrier 10 board surface, such as Figure 5 As shown, the carrier 10 has a metal substrate 11, an insulating layer 12 and a copper foil layer 13 are arranged on the surface of the metal substrate 11 in turn, and at least one metal substrate 11 is exposed on the surface of the carrier 10. In the open area 14 , at least one chip 21 is fixed on the metal substrate 11 in the open area 14 .
[0040] The copper foil layer 13 is also divided into at least two blocks 13, and at least one external power contact 132 is respectively formed on the predetermined two blocks 131, and each chip 21 is respectively fixed on the metal substrate 11 in the open area 14. , and respectively fixed on the predetermined blocks 131 of the copper foil layer 13, and are directly or indirectly electrically connected 131 to the block to wh...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More - R&D
- Intellectual Property
- Life Sciences
- Materials
- Tech Scout
- Unparalleled Data Quality
- Higher Quality Content
- 60% Fewer Hallucinations
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com
