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Improved scan chain unit and online testing method based on improved scan chain unit and clock control logic

A scanning chain and scanning data technology, which is applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problem that the circuit state cannot be saved, and achieve good application value and small time redundancy.

Active Publication Date: 2013-09-11
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Hussain Al-Asaad proposed a new scan chain unit in the literature, which solves the problem that the circuit state cannot be saved during the online test
But this method can only be used for non-concurrent testing, and each group of vectors can only work for one clock cycle

Method used

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  • Improved scan chain unit and online testing method based on improved scan chain unit and clock control logic
  • Improved scan chain unit and online testing method based on improved scan chain unit and clock control logic
  • Improved scan chain unit and online testing method based on improved scan chain unit and clock control logic

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Experimental program
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specific Embodiment approach 1

[0040] Specific implementation mode 1: the following combination figure 1 , figure 2 , image 3 with Picture 9 To describe this embodiment, the improved scan chain unit described in this embodiment is characterized in that the improved scan chain unit 1 includes a first selector 1-1, a second selector 1-2, and a third selector 1. -3. Fourth selector 1-4, test trigger 1-5 and function trigger 1-6,

[0041] The enable terminal input signal of the first selector 1-1 is mode[1], the enable terminal input signal of the second selector 1-2 is mode[0], and the enable terminal input of the third selector 1-3 The signal is mode[0], and the enable terminal input signal of the fourth selector 1-4 is mode[1];

[0042] The 0 input terminal of the first selector 1-1 is used as the test unit scan data input terminal of the improved scan chain unit 1, and the test scan data SI is input. The 1 input terminal of the first selector 1-1 and the second selector 1 The 0 input terminal of -2 is connec...

specific Embodiment approach 2

[0054] Specific implementation manner 2: the following combination Picture 10 This embodiment will be described. This embodiment will further explain the first embodiment. The clock signal TCLK of the test flip-flops 1-5 and the clock signal FCLK of the functional flip-flops 1-6 are generated independent clocks, and the clock signal TCLK is a square wave CLK1. Or set to 0, the clock signal FCLK is a square wave CLK2 or set to 0, and the frequency of the square wave CLK1 and the square wave CLK2 are the same.

[0055] This setting method is used for the clock for non-concurrent testing. When FCLK is in the square wave CLK2 state, the sequential circuit is in normal working state, and at the same time, the test data is moved in; when FCLK is set to 0, the sequential circuit combination part is performed Test; after the test, the test data is removed. This move out operation and the next move in operation are carried out at the same time.

specific Embodiment approach 3

[0056] Specific implementation manner three: the following combination Picture 11 This embodiment will be described. This embodiment will further explain the first embodiment. The clock signal TCLK of the test flip-flops 1-5 and the clock signal FCLK of the functional flip-flops 1-6 are generated independent clocks, and the clock signal TCLK is a square wave CLK1. Or set to 0, the clock signal FCLK is a square wave CLK2, and the frequency of CLK1 is 2-10 times the frequency of CLK2.

[0057] This setting method is used for the clock during concurrent testing. FCLK is always in the state of square wave CLK2, that is, the sequential circuit is always in normal working state. When the test data is moved in, the test of the combination part of the sequential circuit is completed by one cycle of FCLK , After the test is over, move out the test data. This move out operation and the next move in operation are carried out at the same time.

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Abstract

The invention discloses an improved scan chain unit and an online testing method based on the improved chain unit and a clock control logic, belongs to the technical field of digital integrated circuit SOC (System On Chip) tests and aims at solving the problems that a current method for online test of the completeness of a sequence circuit is only used for a non-concurrent test and each group of vector can work for one clock cycle. According to the invention, an input end 1 of a first selector of the improved scan chain unit is connected with an input end 0 of a second selector; an input end 1 of the second selector is connected with an input end 0 of the first selector; the output end of the first selector is connected with an end D of a test trigger; an end Q of the test trigger is connected with an input end 0 of a third selector; the end Q of the test trigger is also connected with an input end 1 of a fourth selector; the output end of the second selector is connected with an end D of a function trigger; an end Q of the function trigger is connected with an input end 0 of the fourth selector; and the end Q of the function trigger is also connected with an input end 1 of the third selector.

Description

Technical field [0001] The invention relates to an improved scan chain unit and an online testing method based on the improved scan chain unit and clock control logic, and belongs to the technical field of digital integrated circuit SOC testing. Background technique [0002] With the improvement of integrated circuit technology, complex systems composed of multiple chips can be integrated on one chip, and System-on-a-Chip (SOC) has emerged at the historic moment. In view of the reliability requirements of system chips, SOC testing issues have been extensively studied. According to the different testing phases, SOC testing can be divided into offline testing and online testing [1]. Offline testing refers to testing performed when the system is not working. Typical offline testing methods include scan design, boundary scan design and built-in self-test (Build-in-Self-Test, BIST). Scan design can well realize the observability of the internal state of the sequential circuit. Some...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3185
Inventor 俞洋彭喜元彭宇王帅王继业
Owner HARBIN INST OF TECH