Improved scan chain unit and online testing method based on improved scan chain unit and clock control logic
A scanning chain and scanning data technology, which is applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problem that the circuit state cannot be saved, and achieve good application value and small time redundancy.
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specific Embodiment approach 1
[0040] Specific implementation mode 1: the following combination figure 1 , figure 2 , image 3 with Picture 9 To describe this embodiment, the improved scan chain unit described in this embodiment is characterized in that the improved scan chain unit 1 includes a first selector 1-1, a second selector 1-2, and a third selector 1. -3. Fourth selector 1-4, test trigger 1-5 and function trigger 1-6,
[0041] The enable terminal input signal of the first selector 1-1 is mode[1], the enable terminal input signal of the second selector 1-2 is mode[0], and the enable terminal input of the third selector 1-3 The signal is mode[0], and the enable terminal input signal of the fourth selector 1-4 is mode[1];
[0042] The 0 input terminal of the first selector 1-1 is used as the test unit scan data input terminal of the improved scan chain unit 1, and the test scan data SI is input. The 1 input terminal of the first selector 1-1 and the second selector 1 The 0 input terminal of -2 is connec...
specific Embodiment approach 2
[0054] Specific implementation manner 2: the following combination Picture 10 This embodiment will be described. This embodiment will further explain the first embodiment. The clock signal TCLK of the test flip-flops 1-5 and the clock signal FCLK of the functional flip-flops 1-6 are generated independent clocks, and the clock signal TCLK is a square wave CLK1. Or set to 0, the clock signal FCLK is a square wave CLK2 or set to 0, and the frequency of the square wave CLK1 and the square wave CLK2 are the same.
[0055] This setting method is used for the clock for non-concurrent testing. When FCLK is in the square wave CLK2 state, the sequential circuit is in normal working state, and at the same time, the test data is moved in; when FCLK is set to 0, the sequential circuit combination part is performed Test; after the test, the test data is removed. This move out operation and the next move in operation are carried out at the same time.
specific Embodiment approach 3
[0056] Specific implementation manner three: the following combination Picture 11 This embodiment will be described. This embodiment will further explain the first embodiment. The clock signal TCLK of the test flip-flops 1-5 and the clock signal FCLK of the functional flip-flops 1-6 are generated independent clocks, and the clock signal TCLK is a square wave CLK1. Or set to 0, the clock signal FCLK is a square wave CLK2, and the frequency of CLK1 is 2-10 times the frequency of CLK2.
[0057] This setting method is used for the clock during concurrent testing. FCLK is always in the state of square wave CLK2, that is, the sequential circuit is always in normal working state. When the test data is moved in, the test of the combination part of the sequential circuit is completed by one cycle of FCLK , After the test is over, move out the test data. This move out operation and the next move in operation are carried out at the same time.
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