Clock generation circuit

Abstract

The invention provides a clock generating circuit. The clock generation circuit includes: a first frequency divider; a loop unit having a second frequency divider and generating an output clock that is phase-synchronous with a reference clock of the first frequency divider and has a frequency that is F times the reference clock a frequency; a clock switching unit that selects one input clock among the plurality of input clocks and supplies the selected input clock to the first frequency divider; and a timing control unit. The timing control unit switches the clock selection command according to the switching of the clock selection information, switches at least one of the setting of the number R of the input clock and the setting of the number F of the output clock, and starts using the first frequency division after switching the setting counting operation of the frequency divider and counting operation using the second frequency divider.

Description

technical field [0001] The present invention relates to a clock generation circuit using a PLL (Phase Locked Loop). Background technique [0002] A PLL is a circuit that generates a phase-locked clock from an input signal, and has been used in various fields. Figure 12 It is a block diagram illustrating the general structure of a PLL. exist Figure 12 Among them, the frequency divider 1 divides the input clock CLKI by a predetermined frequency division ratio 1 / R, and outputs the reference clock CLKREF having a frequency of 1 / R of the input clock CLKI to the phase comparator 3 of the loop unit 2 . The loop unit 2 is a circuit in which a phase comparator 3 , a loop filter 4 , a VCO (Voltage Controlled Oscillator) 5 , and a frequency divider 6 are connected in a loop form. Here, the phase comparator 3 compares the phases of the reference clock CLKREF and the feedback clock CLKFB output from the frequency divider 6, and outputs a phase error signal representing a phase error b...

AI Technical Summary

Problems solved by technology

If the reference clock CLKREF having a large phase difference with respect to the feedback clock CLKFB is output to the phase comparator 3, a large phase error signal is generated and thus the PLL loses synchronization

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