Instruction set optimization method for dynamically reconfigurable processors
An optimization method and processor technology, applied in the direction of machine execution devices, etc., can solve the problem that the function of the computing unit is not too high, and achieve the effect of reducing dynamic power consumption and minimizing the overall flip probability
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[0026] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0027] refer to figure 1 , shows a flow chart of an optimization method for an instruction set of a dynamically reconfigurable processor according to the present invention, specifically including:
[0028] Step S101, the instruction set architecture is applied to program the array of operation units of the dynamically reconfigurable processor;
[0029] Step S102, the instruction set adopts equal-length operation codes;
[0030] Step S103, the encoding method of the instruction set for the operation code adopts a discrete encoding method that matches the hardware;
[0031] In step S104, the encoding of the instruction set refers to the usage frequency of each operation code.
[0032] The instruction set architecture is the core ...
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