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Instruction set optimization method for dynamically reconfigurable processors

An optimization method and processor technology, applied in the direction of machine execution devices, etc., can solve the problem that the function of the computing unit is not too high, and achieve the effect of reducing dynamic power consumption and minimizing the overall flip probability

Active Publication Date: 2014-04-16
TSINGHUA UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, dynamically reconfigurable processors are usually used for a large number of repeated parallel operations, so there is no high requirement for the function of the operation unit

Method used

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  • Instruction set optimization method for dynamically reconfigurable processors
  • Instruction set optimization method for dynamically reconfigurable processors
  • Instruction set optimization method for dynamically reconfigurable processors

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Embodiment Construction

[0026] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0027] refer to figure 1 , shows a flow chart of an optimization method for an instruction set of a dynamically reconfigurable processor according to the present invention, specifically including:

[0028] Step S101, the instruction set architecture is applied to program the array of operation units of the dynamically reconfigurable processor;

[0029] Step S102, the instruction set adopts equal-length operation codes;

[0030] Step S103, the encoding method of the instruction set for the operation code adopts a discrete encoding method that matches the hardware;

[0031] In step S104, the encoding of the instruction set refers to the usage frequency of each operation code.

[0032] The instruction set architecture is the core ...

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Abstract

The invention provides an instruction set optimization method for dynamically reconfigurable processors. The method comprises the following steps that: an instruction set architecture is applied to the programming of an operating unit array of a dynamically reconfigurable processor; equilong operation codes are adopted to an instruction set; the encoding mode of the instruction set is a discrete encoding mode matched with hardware; and codes of the instruction set refer to the use frequency of each operation code, and based on a simple instruction, operations such as rounding shift, saturation operation and conditional operation which are frequently used in video decoding application are added, thereby avoiding the occurrence of complex configuration information and low efficiencies caused by implementing the operations above by software.

Description

technical field [0001] The invention relates to the technical field of dynamically reconfigurable processors, in particular to an optimization method for an instruction set of a dynamically reconfigurable processor. Background technique [0002] Dynamic reconfigurable processor is a new type of processor architecture, which combines the flexibility of software and the efficiency of hardware. Compared with traditional single-core microprocessors, it can not only change the control flow, but also change the data path. It has the advantages of high performance, low power consumption, good flexibility, and good scalability, and is especially suitable for processing computationally intensive algorithms, such as media processing, pattern recognition, and baseband processing. Therefore, dynamically reconfigurable processors have also become an important development direction of the current processor structure, such as the ADRES processor of the European Microelectronics Center (IME...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30
Inventor 朱敏刘雷波王延升朱建峰杨军曹鹏时龙兴尹首一魏少军
Owner TSINGHUA UNIV