Memory array cell information read method and system thereof

Abstract

The present invention provides a memory array cell information read method and a system thereof. The method comprises: concurrently gating a plurality of continuous bit lines including bit lines of a read cell; applying first read voltage on one bit line of a read and memory cell, and applying second read voltage on the other bit line, wherein the second read voltage is higher than the first read voltage; applying voltage on a bit line adjacent to the bit line of the read and memory cell, wherein the bit line of the read and memory cell is applied with the first read voltage, the applied voltage is the same as the first read voltage; comparing the electric current generated by the read and memory cell with the preset electric current value, and determining the memory information of the read and memory cell. According to the present invention, during reading the information, the read electric current is only generated on the read and memory cell, the electric potential difference between the read and memory cell and the other memory cells does not exist, wherein the other memory cells are the cells adjacent to the bit line applied with the low voltage, such that the improvement of the source electrode voltage of the read and memory cell can not be generated due to the current leakage, the requirement time of the grid electrode voltage increasing of the read and memory cell is not affected so as to improve the information read speed of the memory cell, wherein the grid electrode voltage is required to increase to a certain degree until the level is opened.

Description

technical field [0001] The invention relates to the field of information storage, in particular to a storage array unit information reading method and system. Background technique [0002] The core of the entire memory is an array of storage cells. For the method of reading the information of the storage cells in the array, refer to figure 1 , the storage unit takes an ordinary MOS transistor as an example, each storage unit (cell) has three ports, one of which is a control port, which is equivalent to the gate of an ordinary MOS transistor, and the other two ports are equivalent to the source and drain of an ordinary MOS transistor pole. The control ports of the memory cells are connected to the word line, and the control ports of the memory cells in the same row of the array are connected to the same word line WL1. The sources and drains of memory cells in the same row in the memory array are connected end to end in sequence, and the sources and drains of two adjacent me...

AI Technical Summary

Problems solved by technology

[0005] The invention solves the problem that the speed of the existing memory array unit information reading method is slow

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