Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for manufacturing semiconductor structure

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effects of simple operation, improved mobility, and strong industrial applicability

Active Publication Date: 2012-05-09
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
View PDF4 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, materials commonly used to apply stress to field effect transistors, such as nitride materials, can only provide tensile stress at high temperatures, which limits the application of SMT technology to n-type field effect transistors.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for manufacturing semiconductor structure
  • Method for manufacturing semiconductor structure
  • Method for manufacturing semiconductor structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0024] Hereinafter, the present invention is described by means of specific embodiments shown in the drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.

[0025] Top, cross-sectional, and perspective views of various structures of semiconductor structures according to embodiments of the invention are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a method for manufacturing a semiconductor structure. The method comprises the following steps of: providing a p-type field effect transistor, wherein the transistor comprises a grid on a substrate; forming a tensile stress layer on the transistor; patterning the tensile stress layer, so that a pressure stress is generated in the channel of the transistor; and annealing to memorize the pressure stress in the channel of the transistor and fulfill the purpose of enhancing the performance of the transistor. According to the method, the pressure stress in the channel of the transistor is memorized by using a stress memory technology, so that the mobility of holes is improved and the integral performance of the semiconductor structure is improved.

Description

technical field [0001] The present invention generally relates to a method for manufacturing a semiconductor structure, and more specifically, relates to a method for manufacturing a high-performance semiconductor structure using stress memory technology. Background technique [0002] It is known that applying stress to field effect transistors (FET: field effect transistors) can improve their performance. When stress is applied to a FET, tensile stress can increase electron mobility (or nFET drive current), while compressive stress can increase hole mobility (or pFET drive current). [0003] One way to provide such stress is called stress memory technology (SMT: stressmemorization technique), which includes forming an inherently stressed material (eg, silicon nitride) and annealing various parts of the semiconductor structure, such as above the channel region Stress is memorized in corresponding parts (such as gate region or extension region), and then the stress material ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/31H01L21/311
CPCH01L21/823807H01L29/7847
Inventor 朱慧珑
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com