Method for manufacturing semiconductor structure

Abstract

The invention discloses a method for manufacturing a semiconductor structure. The method comprises the following steps of: providing a p-type field effect transistor, wherein the transistor comprises a grid on a substrate; forming a tensile stress layer on the transistor; patterning the tensile stress layer, so that a pressure stress is generated in the channel of the transistor; and annealing to memorize the pressure stress in the channel of the transistor and fulfill the purpose of enhancing the performance of the transistor. According to the method, the pressure stress in the channel of the transistor is memorized by using a stress memory technology, so that the mobility of holes is improved and the integral performance of the semiconductor structure is improved.

Description

technical field [0001] The present invention generally relates to a method for manufacturing a semiconductor structure, and more specifically, relates to a method for manufacturing a high-performance semiconductor structure using stress memory technology. Background technique [0002] It is known that applying stress to field effect transistors (FET: field effect transistors) can improve their performance. When stress is applied to a FET, tensile stress can increase electron mobility (or nFET drive current), while compressive stress can increase hole mobility (or pFET drive current). [0003] One way to provide such stress is called stress memory technology (SMT: stressmemorization technique), which includes forming an inherently stressed material (eg, silicon nitride) and annealing various parts of the semiconductor structure, such as above the channel region Stress is memorized in corresponding parts (such as gate region or extension region), and then the stress material ...

AI Technical Summary

Problems solved by technology

However, materials commonly used to apply stress to field effect transistors, such as nitride materials, can only provide tensile stress at high temperatures, which limits the application of SMT technology to n-type field effect transistors.

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