Method and device for increasing efficiency of DDR (Double Data Rate) controller

A controller and efficiency technology, applied in the field of data communication, can solve the problems of unserviceable commands, increased data delay, and inability to take into account the input sequence of user commands before and after, to achieve the effect of saving space consumption and improving efficiency

Active Publication Date: 2015-01-28
SANECHIPS TECH CO LTD
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AI Technical Summary

Problems solved by technology

The focus of this strategy is only on the operation efficiency of DDR, and it cannot take into account the input sequence of user commands before and after. It is easy to cause the previously entered commands to be out of service for a long time, resulting in increased data delay, or a large amount of data is backlogged in the static cache. , wasting static cache resources

Method used

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  • Method and device for increasing efficiency of DDR (Double Data Rate) controller
  • Method and device for increasing efficiency of DDR (Double Data Rate) controller
  • Method and device for increasing efficiency of DDR (Double Data Rate) controller

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Embodiment Construction

[0051] It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0052] figure 2 Shown is the flow process of the method for improving DDR controller efficiency in one embodiment of the present invention, and this flow process comprises the following steps:

[0053] Step S10, cache and manage user commands in queue form in time sequence; in one embodiment, a shift register can be used to cache and manage user commands in queue form in time sequence, for example, when multiple user commands are input, the Each storage unit in the shift register is sequentially buffered. In a specific example, the shift register not only has a command output port at the head, but each storage unit also has a command output port, which can output commands sequentially from the head of the queue to the tail of the queue, and can also randomly extract commands for output.

[0054]Step S20, other orde...

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Abstract

The invention relates to the field of data communication and provides a method for increasing efficiency of a DDR (Double Data Rate) controller. The method comprises the following steps of caching and managing user commands in the form of queue according to a time sequence; comparing other commands in the queue with the current operation command to obtain relationships between the other commands and the current operation command; preferentially extracting a command which shares bank and row with the current operation command and outputting the command to a double data rate synchronous dynamic cache DDR when the first input command is in a waiting state. The invention also provides a device for increasing efficiency of the DDR controller. By using the device or method for increasing efficiency of the DDR controller, provided by the invention, the data output delay can be reduced while the bandwidth efficiency of the DDR is increased, and the space consumption of internal static cache is saved.

Description

technical field [0001] The invention relates to the technical field of data communication, in particular to a method and a device for improving the efficiency of a DDR controller. Background technique [0002] At present, the bandwidth required for high-speed data storage is increasing. DDR (Double Data Rate, double data rate synchronous dynamic cache) has become a commonly used device in the field of data storage due to various factors such as price. However, due to the time parameter constraints caused by the refresh operation inside the DDR and various internal structures, the overall bandwidth utilization rate is not high. [0003] In the operation of DDR, when the relationship between adjacent commands is the same as BANK (storage bank) and ROW (row), you can send read or write commands continuously without sending additional commands, so you don’t have to wait for the corresponding delay, and finally you can Long-term effective data appears on the data bus of DDR, whi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/22
Inventor 叶绍镇徐健
Owner SANECHIPS TECH CO LTD
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