32results about How to "Output delay is small" patented technology

The device consists of cascade multiframe detection circuit for carry on sequence number locking detection, cascade sequence automatic regulation circuit for regulating reservoir sequence based on sequence number of each different reservior in cascade set to make it be in accordance with its sequence at transmission end, buffer zone for making zone as per sequence number of reservior and cascade multiframe, write control circuit for writing content in sequenced reservior to relevant buffer zone, read control repositioning and adaptive circuit for regulating frequency and plase of reservoir and read control circuit for reading out data from buffer zone to finalize restoration of cascade as per command of abovesaid circuit.

The invention is a circuit for realizing direction two-dimension discrete wavelet transition, which belongs to image data processing technology field, especially relates to hardware realization of direct two-dimension discrete wavelet transition. The aim is to decrease hardware cost and system delay, and it can be applied to very large scale integration circuit structure design of high speed and low power direct two-dimension discrete wavelet transition of all limit length filters, the invention includes selector, data series and parallel converting interface circuit, primary converting circuit which are connected in order electrically; the primary converting circuit is 4 input and 4 output structure, includes the first parallel filter and the second parallel filter, the first vertical filter and the second vertical filter connected to them and output coefficient regulating unit, the parallel and vertical filters are 2 input and 2 output structure, the first vertical filter and the second vertical filter output is connected to the output coefficient regulating unit; one output electric signal of the output coefficient regulating unit is connected to an external memory, the latter is outputted to one input end of the selector.

The encoding device for HS-SCCH channel makes the output data compact, reduces time delay, and raises circuit usage. The device includes first process circuit and second process circuit. The first process circuit includes the first convolutional coding unit (CCU), and first rate adaption unit (RAU). The first CCU encodes the input data; and RAU carries out rate matching or XOR process for the data, which are than outputted. Characters are that providing enable signal for the first process circuit to read next set of input data, the second process circuit includes following units: connected insequence CRC16 circuit unit, second CCU, second RAU, counter monitoring unit, and time delay compensation unit located at one or several positions: in front of CRC16 circuit unit, between CRC16 circuit unit and second CCU, and between second CCU and second RAU.

The invention discloses a low-latency audio output method for Android applications on a Linux platform. The audio output mode is determined by obtaining the type of audio player used by an Android application in an Android compatible environment in a Linux system, and different output modes can effectively reduce The process involved in the audio playback process of the Android application is reduced, the data interaction between the processes is reduced, the audio output efficiency of the Android application is effectively improved, the output delay is reduced, and the user experience is improved.

A radiation-resistant flip-flop circuit structure based on a single-phase clock, including a clock generation module, a data filtering module, a first single-phase clock basic flip-flop module, a second single-phase clock basic flip-flop module, a third single-phase clock Bit clock basic trigger module, first DICE hardening module, second DICE hardening module, third DICE hardening module, first C-unit module, second C-unit module, third C-unit module and election module. The flip-flop circuit structure of the present invention adopts single-phase clock technology. Compared with the existing flip-flop technology, it not only saves the area cost and reduces power consumption, but also avoids the timing redundancy in the flip-flop of the master-slave structure, and improves the efficiency of the flip-flop. Timing performance, in addition, the trigger circuit structure of the present invention adopts a hybrid DICE+TMR structure, which improves the trigger pulse of the trigger and enhances the ability to resist single event reversal and single event pulse.

The invention relates to the field of data communication and provides a method for increasing efficiency of a DDR (Double Data Rate) controller. The method comprises the following steps of caching and managing user commands in the form of queue according to a time sequence; comparing other commands in the queue with the current operation command to obtain relationships between the other commands and the current operation command; preferentially extracting a command which shares bank and row with the current operation command and outputting the command to a double data rate synchronous dynamic cache DDR when the first input command is in a waiting state. The invention also provides a device for increasing efficiency of the DDR controller. By using the device or method for increasing efficiency of the DDR controller, provided by the invention, the data output delay can be reduced while the bandwidth efficiency of the DDR is increased, and the space consumption of internal static cache is saved.

The invention discloses a low-delay 8B / 10B encoding method and device, which improves the traditional four-channel 8B / 10B encoder, and derives the polarity generation method according to the causal relationship of the 8B / 10B encoding table. The polarity generation part is added to the traditional multi-channel encoder, which saves a lot of waiting time between the internal channels of the traditional multi-channel encoder, improves the efficiency of parallel encoding, and reduces the encoding output delay while increasing the data transmission rate. The present invention can be simply extended to low-latency 8B / 10B encoders of any channel.

The present invention discloses a target simulator real-time drive system based on a DVI interface of a graphics card. The system comprises: a DVI transmission interface, used for establishing a data communication with a graphic workstation and a target simulator; a synchronous transmission control module, used for sending a simulation start signal to a dynamic scene image simulation module based on a field frequency signal output by the DVI transmission interface, and establishing synchronous data transmission with the target simulator; and the dynamic scene image simulation module, used for performing simulation analysis on to-be-tested dynamic scene data acquired from an external device based on the simulation start signal, and storing simulation image data into a frame cache. The present invention further discloses a target simulator real-time drive method based on a DVI interface of a graphics card. The technical scheme provided by the present invention shortens radiation scene output delay, ensures delay stability and thus greatly improves confidence of semi-physical dynamic scene simulation.