A fpga implementation system based on low-latency lz lossless compression algorithm
A lossless compression and realization system technology, applied in the field of FPGA realization system, can solve the problems of not giving full play to the advantages of hardware, small search window, low compression rate, etc., to improve the defects of uncertain output delay, stable output delay, The effect of fast compression
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[0040] Below in conjunction with accompanying drawing, the technical content of invention is described in detail:
[0041] Such as figure 1As shown, the present invention discloses a FPGA implementation system based on a low-latency LZ lossless compression algorithm, including an input buffer module, an output buffer module, a shift register, a readback control module, a matching search module, a character length calculation module, A matching length calculation module and an output control module; the input buffer module is connected with the shift register and the readback control module respectively and then connected with the matching search module, and the matching search module is respectively connected with the character length calculation module and the matching length calculation module and then connected with the output The control module is connected, and the output control module is connected with the output buffer module; the input buffer module is used for buffer...
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