A fpga implementation system based on low-latency lz lossless compression algorithm

A lossless compression and realization system technology, applied in the field of FPGA realization system, can solve the problems of not giving full play to the advantages of hardware, small search window, low compression rate, etc., to improve the defects of uncertain output delay, stable output delay, The effect of fast compression

Active Publication Date: 2019-05-21
中电莱斯信息系统有限公司
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AI Technical Summary

Problems solved by technology

However, the search window of the existing implementation method is small, resulting in low compression rate and low rate, and the advantages of hardware are not fully utilized.

Method used

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  • A fpga implementation system based on low-latency lz lossless compression algorithm
  • A fpga implementation system based on low-latency lz lossless compression algorithm
  • A fpga implementation system based on low-latency lz lossless compression algorithm

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Embodiment Construction

[0040] Below in conjunction with accompanying drawing, the technical content of invention is described in detail:

[0041] Such as figure 1As shown, the present invention discloses a FPGA implementation system based on a low-latency LZ lossless compression algorithm, including an input buffer module, an output buffer module, a shift register, a readback control module, a matching search module, a character length calculation module, A matching length calculation module and an output control module; the input buffer module is connected with the shift register and the readback control module respectively and then connected with the matching search module, and the matching search module is respectively connected with the character length calculation module and the matching length calculation module and then connected with the output The control module is connected, and the output control module is connected with the output buffer module; the input buffer module is used for buffer...

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Abstract

The invention discloses an FPGA realization system of LZ lossless compression algorithm based on a low delay. The system comprises an input cache module, an output cache module, a shift register, a read-back control module, a matching search module, a character length calculation module, a matched length calculation module, and an output control module. The input cache module is used for caching input source data and addressing. The output cache module is used for caching output compressed data. The shift register is used for converting the input source data into 4-bit data needed by hash function calculation through shift. The read-back control module is used for carrying out read-back to obtain source data matched with a search need. The matching search module is used for carrying out matching searching of source data word-by-word hash calculation. The character length calculation module is used for calculating the length of a character which can be not matched in a compressed sequence. The matched length calculation module is used for calculating the length of the matched character in the compressed sequence.

Description

technical field [0001] The invention relates to the field of data compression, in particular to an FPGA implementation system based on a low-delay LZ lossless compression algorithm. Background technique [0002] With the advent of the information age, people are becoming more and more dependent on data, and the amount of data exchange is increasing day by day. Massive data brings large-scale data transmission and storage requirements. Effectively compressing data can reduce the space required for storage and maximize the use of limited communication bandwidth. Moreover, the compressed data encrypts the original data to a certain extent, thereby further improving data security. [0003] However, many data compression and decompression solutions today are implemented based on software. There is a fatal weakness in software compression and decompression, that is, it consumes too much precious CPU resources and is slow. In addition, the system is unstable, and it is difficult...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M7/42
CPCH03M7/42
Inventor 许建峰茅文深刘文松周全宇姚浩
Owner 中电莱斯信息系统有限公司
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