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Method for chip to wafer bonding

A chip and wafer technology, applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problem of expensive chip scrapping and achieve the effect of precise flat surface

Active Publication Date: 2012-05-30
EV GRP E THALLNER GMBH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The handling of the base wafer is therefore of great importance, since the breakage of the base wafer shortly before separating the stack of multiple chips on the wafer can result in the scrapping of thousands of expensive chips

Method used

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  • Method for chip to wafer bonding
  • Method for chip to wafer bonding
  • Method for chip to wafer bonding

Examples

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Embodiment Construction

[0047] The same components and components with the same function are identified with the same reference symbols in these figures.

[0048] exist figure 1 A schematic configuration of an apparatus for carrying out the method according to the invention is shown in , where the base wafer 1 is mounted or otherwise premounted, for example, on a carrier 5 at station B.1 and is removed at station B.2 After peeling off the back grinding film (back grinding tape (back grinding tape)) that existed from the previous back grinding process, in area A Figure 2f The chip layer is placed on the base wafer 1 .

[0049] The handling of the carrier 5 with the base wafer 1 takes place via a robot B.3 with a robot arm R.

[0050] Arranged on the handling module B is a cassette station B. 4 , from which the materials and / or components required for the method of producing the chip stack 16 are extracted or redistributed.

[0051] After the chips have been placed in the chip placement system A, t...

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PUM

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Abstract

The invention relates to a method for bonding a plurality of chips (3) to a base wafer (1) which contains chips (3') on the front side, wherein the chips (3) are stacked in at least one layer on the rear side of the base wafer (1), and wherein electrically conductive connections are established between the vertically adjacent chips (3, 3'). Said method comprises the following steps: a) the front side (2) of the base wafer (1) is fixed to a carrier (5),b) at least one layer of chips (3) is placed in a defined position on a rear side (6) of the base wafer (1),and c) the chips (3, 3') on the base wafer (1) fixed to the carrier (5) are thermally treated. Said method is characterised in that prior to step c), the chips (3') on the base wafer (1) are at least partially separated into stacked chip sections (1 c) on the base wafer.

Description

technical field [0001] The invention relates to a method according to claim 1 . Background technique [0002] Due to the miniaturization pressures prevailing in the semiconductor industry, there is a need for methods that can be used to manufacture so-called "3D integrated chips" (3D ICs). A 3D IC consists of a chip stack in which multiple chips are stacked vertically on top of each other and there are connections through the silicon to vertically adjacent chips. These connections are called "Through Silicon Via (Through Silicon Via)" (TSV). [0003] People expect such chips to have higher packing density and higher efficiency at lower cost. Among other things, new types and forms of chips can thus be produced. For the manufacture of 3D ICs different methods are in principle considered, namely the time-consuming stacking of individual chips onto individual chips, also known as the "chip-to-chip" (C2C) method, or the stacking of wafers on wafers, also known as "Wafer-to-W...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/98H01L25/065
CPCH01L2224/83805H01L24/83H01L2221/68381H01L24/94H01L2224/81005H01L2224/81065H01L2224/81205H01L2224/94H01L2221/68331H01L2224/8082H01L2224/80907H01L2224/32225H01L2224/80075H01L2224/83205H01L24/74H01L2224/74H01L2224/73204H01L24/81H01L2224/80006H01L2924/01322H01L24/32H01L2224/08225H01L2224/83005H01L24/97H01L2221/68304H01L25/50H01L24/80H01L25/0657H01L2224/0557H01L2221/68327H01L2224/80815H01L2224/81075H01L2224/83907H01L2224/81907H01L2224/80805H01L2924/15738H01L2224/8382H01L2224/97H01L2224/16225H01L2224/81805H01L21/6835H01L2924/15311H01L2224/80205H01L2224/7598H01L2224/80065H01L2224/81815H01L21/568H01L2225/06568H01L2224/83065H01L21/6836H01L2225/06541H01L2224/0401H01L2224/06181H01L2224/8182H01L2224/83075H01L2225/06513H01L24/08H01L24/16H01L2224/83815H01L23/3128H01L21/561H01L21/563H01L2924/00014H01L2924/0002H01L2924/12042H01L2924/14H01L2224/81H01L2224/80H01L2224/83H01L2924/01014H01L2924/00H01L2224/05552H01L21/50
Inventor M.温普林格
Owner EV GRP E THALLNER GMBH