Layout bipartition method

Abstract

The invention discloses a layout bipartition method, aiming at solving the defect that the product quality is lowered due to overlarge layout density in the conventional photoetching technology. The layout bipartition method disclosed by the invention comprises the following steps of: partitioning graphs of which the graph pitch is less than a minimal photoetching pitch, into two sub layouts, and obtaining a layout graph through two photoetching operations; when the graph pitch in the sub layout is still less than the minimal photoetching pitch after two sub layouts are formed, partitioning the graphs in the layouts into at least two sub graphs, partitioning each sub graph of which the pitch is less than the minimal photoetching pitch, into two sub layouts by using the sub graph as a unit, and obtaining the layout graph after carrying out two photoetching operations on a substrate; and labeling the layout region where sub layouts cannot be obtained by using a partitioning method. The layout bipartition method disclosed by the invention is applied to the fields of layout design and product manufacture of large-scale integration circuits, and has the characteristics of convenience for use and high accuracy.

Description

technical field [0001] The present invention relates to a version Figure II division method. Background technique [0002] In the mainstream microelectronics manufacturing process, photolithography is an indispensable process, and it is also the most complex, expensive and critical process. In the manufacturing process of integrated circuits, dozens of photolithography processes are often required. At present, the mainstream technology of integrated circuit manufacturing process is photolithography technology using ultraviolet light including far ultraviolet light as light source. With the development of chips in the direction of smaller size and higher density, lithography technology has also encountered new challenges. For the 32nm / 22nm layout, due to the small size and high density of the pattern, the pattern on the photoresist will be deformed under the existing photolithography technology, which will seriously affect the quality of chip manufacturing. The new photol...

AI Technical Summary

Problems solved by technology

For the 32nm / 22nm layout, due to the small size and high density of the pattern, the pattern on the photoresist will be deformed under the existing photolithography technology, which will seriously affect the quality of chip manufacturing

The new photolithography technology, including extreme ultraviolet technology and immersion argon fluoride technology, has no good prospects in terms of process and production cost.

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