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Method for reducing induction drain electrode leakage of semiconductor device gate

A drain leakage and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as complex processes, reduce drain leakage current, maintain other properties, and reduce band-band tunneling effects Effect

Active Publication Date: 2014-11-19
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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  • Method for reducing induction drain electrode leakage of semiconductor device gate
  • Method for reducing induction drain electrode leakage of semiconductor device gate
  • Method for reducing induction drain electrode leakage of semiconductor device gate

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Embodiment Construction

[0027] The present invention will be further described below in combination with principle diagrams and specific operation examples.

[0028] see figure 2 As shown, the method for reducing gate-induced drain leakage of semiconductor devices in the present invention specifically includes the following steps:

[0029] A layer of sidewall film 1 is grown on a substrate 0 that has completed the shallow trench isolation process (STI) 4 on both sides. The sidewall film 1 can be a silicon oxide or silicon nitride film, and the source and gate of the substrate There are low-doped source and drain regions (LDD) 8 at the junction of the drain and the gate respectively, such as Figure 3A As shown, ion implantation 5 is performed on the side wall film 1 from the incident point facing the source 6 and forms a certain angle α with the vertical direction. In a specific embodiment, the implantation angle α can be selected between 15 degrees and 30 degrees. any angle. In a specific embodi...

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Abstract

The invention discloses a method for reducing induction drain electrode leakage of a semiconductor device gate, wherein the method comprises the following steps of: growing one layer of side wall film on a substrate two sides of which are subjected to shallow trench isolation; carrying out ion implantation forming a certain angle with a vertical direction on the side wall film above a source electrode and a drain electrode; etching the side wall film, forming a side wall on the semiconductor device gate, regulating a side wall etching menu to ensure that the width of the source electrode of the etched side wall is reduced and the width of the drain electrode is increased; and carrying out source electrode and drain electrode heavy doping and annealing processes. According to the invention, under the condition of keeping the effective length of a trench unchangeable, the strength of a longitudinal electric field is reduced, thus the drain electrode leakage current of the semiconductor device gate is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor preparation, in particular to a method for reducing gate-induced drain leakage of semiconductor devices. Background technique [0002] Gate-Induced Drain Leakage (GIDL, Gate-Induced Drain Leakage) means that when the device is off-state (ie Vg=0), if the drain is connected to Vdd (ie Vd=Vdd), Due to the overlap between the gate and the drain, there will be a strong electric field in the overlapping region between the gate and the drain, and the carriers will undergo band-to-band tunneling under the action of the strong electric field. Tunneling), causing leakage current from drain to gate. [0003] The gate-induced-drain leakage current has become one of the main reasons affecting the reliability and power consumption of small-sized MOS devices, and it also has an important impact on the erasing and writing operations of memory devices such as EEPROM. When the process enters the ultra-deep...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
Inventor 俞柳江
Owner SHANGHAI HUALI MICROELECTRONICS CORP