Method for processing video processing tasks by aid of multi-core processing chip and system using method

Abstract

The invention relates to the field of video processing, and discloses a method for processing video processing tasks by the aid of a multi-core processing chip and a system using the method. By the aid of the method and the system using the same, the utilization rate of an HDVICP (high-definition video image co-processor) under a high load is increased, and priority configuration aiming at task queues can be supported. The method includes the steps: building the task queues according to task categories by the aid of a first processing core and allowing other processing cores to add waiting tasks into the task queues; respectively building a service thread for each programmable module and registering a plurality of executive elements respectively including one task queue for each service thread by the aid of the first processing core; and inquiring the task queues according to preset priorities in idle and committing an inquired first task in a first non-empty task queue to the corresponding programmable module for processing by the aid of each service thread.

Description

technical field [0001] The invention relates to the field of video processing, in particular to an embedded video processing technology. Background technique [0002] Netra platform's high-efficiency codec computing capability comes from its high-definition video image coprocessor (HDVICP), whose control is completed by an ARM-CORTEX-M3 processing core (called VID). According to different chip models, the number of HDVICP may be different. As a resource module, VID must uniformly manage all HDVICPs and improve their usage efficiency. [0003] HDVICP can work independently. In the case of multiple HDVICPs, each HDVICP is equal in capability. Except that there is a certain internal competition when accessing DDR, its work flow does not interfere with each other. In the current system, HDVICP can perform but not limited to the following tasks: [0004] A1) Video compression, support standard 264, Hikvision 264 and MPEG4 video compression standards; [0005] A2) Video decodi...

AI Technical Summary

Problems solved by technology

This method has the fastest response speed when the system load is low, but the inventors of the present invention have found that when the system load is high, the effective utilization rate of HDVICP will be reduced, and the priority control will fail, because: in the system When the load is high, HDVICP has a high probability of being busy, causing threads to fail to query idle HDVICP and forced to sleep

The shortest sleep time is 1ms, however, it is possible that after 0.1ms, HDVICP is already in an idle state, and the 0.9ms that the task thread sleeps more is wasted, and HDVICP only works for one or several hours each time. ms, this 0.9ms waste is huge for HDVICP

For priority control, since the first thread to wake up after HDVICP is idle will always get the right to use HDVICP first, the priority set for the task thread will lose its effectiveness

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