Raw wafer grouting encapsulation technology

Abstract

The invention discloses a raw wafer grouting encapsulation technology, relating to a wafer encapsulation technology. The technological process comprises the following steps of: (1) performing grouting by TSV (through silicon via) and RDL (redistribution layer) procedures in the default contact position on a raw wafer according to the need of contact design, plating conductive metal in the grouting hole, and performing CMP (chemical mechanical polishing) for leveling the surface of the raw wafer; (2) performing the procedure of wafer formation on the raw wafer, and making grouting connection of an external contact loop and TSV; (3) after the procedure of wafer formation, generating an external contact on the metal layer, and placing a passivation layer on the surface of the metal layer; and (4) directly placing a solder ball or directly performing Metalbumping, and cutting the wafer into grains. Through the invention, the cost of substrate, wire and glue pouring can be completely reduced, high-density memory encapsulation can be performed without an upper limit, and the limit of the encapsulation space is completely broken through. The whole MCP (multi chip package) or SiP (system in package) is boosted to the wafer-level technology, and an obvious boundary is eliminated between an encapsulation factory and a wafer factory.

Description

Technical field: [0001] The invention relates to a wafer packaging technology, in particular to a bare wafer filling hole packaging technology. Background technique: [0002] Existing wafer-level packaging technologies all process the packaging process after the wafer is completed. Since there are circuits on the wafer, it is impossible to fill the hole due to the obstruction of the line when performing TSV. Even after filling the holes, whether electroplating or vacuum deposition is used, the existing circuit will be damaged to some extent. Since the circuit on the wafer is complete, the insulation effect produced in the filled holes will be an insurmountable problem. If RDL is performed again, the surface of the wafer may be damaged. Invention content: [0003] The purpose of the present invention is to provide a bare wafer filling hole packaging technology, all of its production procedures except RDL and TSV are made on the bare wafer in advance, and there will be no p...

AI Technical Summary

Problems solved by technology

Since the circuit on the wafer is complete, the insulation effect produced in the filled holes will be an insurmountable problem. If RDL is performed again, the surface of the wafer may be damaged.