Integrated circuit front-end verification method

Abstract

The invention discloses an integrated circuit front-end verification method, which includes: establishing a verification platform for a top module to be tested, calling the top module of the verification platform through verification scripts, and establishing a simulation environment used in verification; allowing the verification platform to transmit a header file for configuring parameters of the module to be tested before compiling of the top module to be tested, and configuring the top module to be tested according to configuration of the header file when the top module to be tested is compiled; nesting open interface scripts used before and after simulation, and configuring a simulation environment; appointing parameters used by the verification platform through the interface scripts open to developers by the verification platform; passing the scripts in by regression testing according to the appointed parameters for the verification platform and calling a test case to verify the top module to be tested; and covering all covering points of the top module to be tested according to functional coverage. By the method, burden can be relieved for verification engineers, and verification speed is high.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, packaging and testing, and in particular relates to a front-end verification method of an integrated circuit. Background technique [0002] With the increasing complexity of SOC chip design, the time and resources occupied by functional verification in the SOC design process have reached 60~70%. In order to complete verification more quickly, verifiers need to build an efficient verification environment around the design in order to expect to find as many errors (bugs) as possible in as little time as possible. This requires the verification process to be more automated, and verifiers are required to optimize the verification environment for a certain module to be tested. [0003] An initial understanding of the front-end and back-end in the field of integrated circuits is required here. Among them, the front end is mainly responsible for logic implementation, usually using a ...

AI Technical Summary

Problems solved by technology

[0007] Although some of the existing methods can also realize the automation of verification, as mentioned above, only the verification script calls the top-level module for verification, that is, it is only a layer of environment call

Since the macro parameters (parameters) in the module to be tested can only be modified during compilation, the existing method prevents the parameters in the module to be tested from being dynamically modified by the verification personnel, and can only be modified in the verification platform. This makes the validation less automated

For example, for intellectual property core (IP) design modules, existing methods cannot automatically verify different IP customizations

In addition, the verification script of the existing method is fixed, and there is no interface for the verification engineer to call other scripts, that is, other scripts cannot be nested; when the verification personnel need to optimize the verification environment of a certain module to be tested, they can only modify the existing script. This makes each verifier have to master the internal structure of the existing environment, which increases the burden on the verifier