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Clock reproducing and timing method in a system having a plurality of devices and memory controller with flexible data alignment

A clock generator and clock technology, used in timing and clock, regenerating the clock used in the system, and semiconductor device fields, can solve problems such as inability to use high-speed applications, limited operating frequency range, clock signal distortion, etc.

Inactive Publication Date: 2012-08-01
NOVACHIPS CANADA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When using a common source clock, the clock signal will be distorted due to the parallel nature of this structure
At the same time, it has several skew factors (skew factor), when many devices are connected in the form of multi-point connection, the operating frequency range is limited, and it cannot be used for high-speed applications
Source synchronous clock systems using reclocking and retransmission provide a higher operating frequency range and avoid some common synchronous clock skew factors, but introduce other skew factors that do not seriously affect system performance

Method used

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  • Clock reproducing and timing method in a system having a plurality of devices and memory controller with flexible data alignment
  • Clock reproducing and timing method in a system having a plurality of devices and memory controller with flexible data alignment
  • Clock reproducing and timing method in a system having a plurality of devices and memory controller with flexible data alignment

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Embodiment Construction

[0121] Example embodiments of the invention are described in detail below with reference to the accompanying drawings, which form a part hereof, and in which are shown by way of illustrations specific example embodiments that may be used for practicing the invention. The embodiments have been described in sufficient detail to enable those skilled in the art to practice the invention, however, it is to be understood that other embodiments may be utilized and logical, mechanical, electrical, and other changes may be made without departing from the scope of the invention. Accordingly, the following detailed description is not limiting, and the scope of the invention is defined by the appended claims.

[0122] As mentioned above, multipoint connections and series configurations are well-known design techniques to address density issues.

[0123] Figure 1 shows a system with multiple memory devices connected in a multipoint connection. The system implements a common synchronous cl...

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Abstract

A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90 DEG . The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller.

Description

[0001] and a memory controller with variable data alignment [0002] This application is a divisional application. The original application is a Chinese patent application with an application date of December 4, 2008 and an application number of 200880120501.6. variable data alignment memory controller." [0003] Cross References to Related Applications [0004] This application claims U.S. Provisional Patent Application No. 61 / 013,784, filed December 14, 2007, U.S. Provisional Patent Application No. 61 / 019,907, filed January 9, 2008, U.S. Provisional Patent Application No. 61 / 019,907, filed March 26, 2008 Priority to Application No. 61 / 039,605, U.S. Patent Application No. 12 / 168,091, filed July 4, 2008, and U.S. Patent Application No. 12 / 325,074, filed November 28, 2008. technical field [0005] The present invention relates to devices. In particular, the invention relates to a system having a plurality of devices and a method for regenerating a clock used by the system. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/10G11C7/22
CPCG11C5/025G11C7/1051G11C7/222G11C7/1078H01L2224/73265H01L2224/32145H01L2225/06562H01L25/0657G11C7/20H04L7/0008G11C7/1072G11C7/1093H01L2225/06506G11C7/1066G11C7/02G11C7/22H01L2224/48227H01L2224/48145H01L2225/0651H01L2924/00H01L2924/00012G11C16/32G06F1/10
Inventor 潘弘柏P·吉利厄姆
Owner NOVACHIPS CANADA