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Error detection and correction for external DRAM

An error correction and corresponding technology, applied in error detection/correction, instrumentation, computing, etc., to achieve the effect of high performance and high computing integrity

Active Publication Date: 2012-08-15
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, adding I / O pins and DRAM chips to a processing unit system to support ECC introduces an unnecessary and potentially significant cost burden for many processing unit applications that do not require ECC support

Method used

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  • Error detection and correction for external DRAM
  • Error detection and correction for external DRAM
  • Error detection and correction for external DRAM

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Embodiment Construction

[0028] In the following description, numerous details are set forth in order to provide a deeper understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order not to obscure the invention.

[0029] System Overview

[0030] figure 1 A block diagram of a computer system 100 configured to implement one or more aspects of the invention is shown. The computer system 100 includes a central processing unit (CPU) 102 and a system memory 104 that communicate via a bus path through a memory bridge 105 . Such as figure 1 As shown, memory bridge 105 may be integrated into CPU 102 . Alternatively, the memory bridge 105 may be a conventional device such as a north bridge chip connected to the CPU 102 via a bus. The memory bridge 105 is connected to an I / O (input / output) bridge 107 through...

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PUM

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Abstract

One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input / output (I / O) pins. Eliminating I / O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Patent Application Serial No. 12 / 568,639, filed September 28, 2009, and US Patent Application Serial No. 12 / 568,642, filed September 28, 2009. technical field [0003] The present invention relates generally to error detection and correction in memory systems, and more particularly to error detection and correction to external dynamic random access memory (DRAM). Background technique [0004] Certain processing units include multiple multi-threaded processing cores that can be configured to perform high-throughput, highly parallel computations. One example of a processing unit that includes multi-threaded processing cores is a graphics processing unit (GPU). A GPU can be configured to execute graphics programs that typically require high computational throughput on multi-threaded processing cores to generate real-time graphics images. Because graphics programs and their corresp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/00
CPCG06F11/1048
Inventor 弗雷德·格伦纳沙恩·凯尔约翰·S·蒙提姆
Owner NVIDIA CORP