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Error detection and correction of external DRAM

An error correction and error checking technology, applied in error detection/correction, instrumentation, electrical digital data processing, etc., to achieve high performance and high computational integrity

Active Publication Date: 2016-01-20
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, adding I / O pins and DRAM chips to a processing unit system to support ECC introduces an unnecessary and potentially significant cost burden for many processing unit applications that do not require ECC support

Method used

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  • Error detection and correction of external DRAM
  • Error detection and correction of external DRAM
  • Error detection and correction of external DRAM

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Embodiment Construction

[0028] In the following description, a lot of details will be explained to provide a deeper understanding of the present invention. However, it should be clear to those skilled in the art that the present invention can be implemented without one or more of these specific details. In other instances, well-known features are not described in order to avoid obscuring the present invention.

[0029] System Overview

[0030] figure 1 A block diagram of a computer system 100 configured to implement one or more aspects of the present invention is shown. The computer system 100 includes a central processing unit (CPU) 102 and a system memory 104, and the system memory 104 and the CPU 102 communicate via a bus path through a memory bridge 105. Such as figure 1 As shown, the memory bridge 105 may be integrated into the CPU 102. Optionally, the memory bridge 105 may be a conventional device such as a north bridge chip, which is connected to the CPU 102 via a bus. The memory bridge 105 i...

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PUM

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Abstract

One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input / output (I / O) pins. Eliminating I / O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.

Description

[0001] Cross references to related applications [0002] This application claims the priority of the US patent application with serial number 12 / 568,639 filed on September 28, 2009 and the US patent application with serial number 12 / 568,642 filed on September 28, 2009. Technical field [0003] The present invention generally relates to error detection and correction in memory systems, and particularly to error detection and correction of external dynamic random access memory (DRAM). Background technique [0004] Certain processing units include multiple multi-threaded processing cores that can be configured to perform high-throughput, highly parallel computing. An example of a processing unit that includes a multi-threaded processing core is a graphics processing unit (GPU). The GPU can be configured to execute graphics programs that generally require high computational throughput on multi-threaded processing cores to generate real-time graphics images. Because the graphics progra...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/00
CPCG06F11/1048
Inventor 弗雷德·格伦纳沙恩·凯尔约翰·S·蒙提姆
Owner NVIDIA CORP