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Method for fabricating semiconductor devices with fine patterns

A semiconductor and component technology, applied in the field of semiconductor component preparation

Inactive Publication Date: 2012-08-22
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, double patterning technology requires a second exposure process, which requires very precise alignment technology

Method used

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  • Method for fabricating semiconductor devices with fine patterns
  • Method for fabricating semiconductor devices with fine patterns
  • Method for fabricating semiconductor devices with fine patterns

Examples

Experimental program
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Embodiment Construction

[0039] Figure 1 to Figure 8 A method of manufacturing a semiconductor element 100 having a fine pattern according to an embodiment of the present invention is illustrated. figure 1 It is a cross-sectional view illustrating a semiconductor substrate 11 according to an embodiment of the present invention. In one embodiment of the present invention, a target layer 13 (such as an oxide layer) is first formed on the semiconductor substrate 11 (such as a silicon substrate); afterward, a first photoresist layer is formed through a coating process 21 on the target layer 13 and a second photoresist layer 31 on the first photoresist layer 21 . In one embodiment of the present invention, the second photoresist layer 31 is directly formed on the first photoresist layer 21, that is, the first photoresist layer 21 and the second photoresist layer There is no intermediate layer between the photoresist layers 31 .

[0040] figure 2 An exposure process of an embodiment of the present inv...

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Abstract

The embodiment of the present invention provides a method for fabricating semiconductor devices with fine patterns including the steps of providing a semiconductor substrate, forming a first photoresist layer on the semiconductor substrate, forming a second photoresist layer on the first photoresist layer, and performing an exposing process to change the state of at least one first portion of the first photoresist layer and the state of at least one second portion of the second photoresist layer. The conventional double patterning technique requires that the exposure processes be performed twice, which requires very precise alignment between the two exposure processes. In contrast, the embodiment of the present invention can perform the double patterning process with only one exposure process without requiring the precise alignment between the two exposure processes.

Description

technical field [0001] The invention relates to a method for preparing a semiconductor element with a fine pattern, in particular to a method for preparing a semiconductor element with a fine pattern, which integrates two photoresist layers and one exposure process. Background technique [0002] With the increase of component integration, the photolithography technology of semiconductor process requires higher resolution to meet the precision requirements of components. Photolithography is often used to prepare electronic or optoelectronic components on semiconductor substrates, and the photoresist pattern prepared by photolithography is used as a mask for etching or ion implantation. Therefore, the degree of component integration depends on the fineness of the photoresist pattern. [0003] One of the ways to increase the resolution is to use a shorter wavelength light source, such as deep ultraviolet light (wavelength 248 nm) produced by krypton fluoride (KrF) laser or dee...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/027G03F7/00
CPCH01L21/0274H01L21/31144G03F7/094G03F7/095
Inventor 危明康黄沛霖王逸铭曾盈崇
Owner NAN YA TECH