Frequency generation circuit used for generating output frequency signal and related method

Abstract

The invention relates to a frequency generation circuit used for generating an output frequency signal, which comprises a pulse generator, a counter, a processing unit and a frequency generator, wherein the pulse generator is used for generating a first pulse signal; the counter is coupled to the pulse generator; after the first pulse signal is generated by the pulse generator, the counter begins to count by using a reference frequency signal so as to generate a counting value; the processing unit is coupled to the counter and used for receiving the counting value, and when the counting value reaches a critical value, a second pulse signal is generated; and the frequency generator is coupled to the pulse generator and the processing unit and used for generating an output frequency signal according to the first pulse signal and the second pulse signal.

Description

technical field [0001] The invention relates to a frequency generating circuit, in particular to a frequency generating circuit capable of generating a specific duty cycle and related methods. Background technique [0002] For some circuits, such as switched capacitor circuits (switching-capacitor circuit) or double data rate (Double Data Rate, DDR) dynamic random access memory (Dynamic Random-Access Memory, DRAM), the duty cycle of the frequency signal (Duty cycle) is very important. If the duty cycle of the frequency signal deviates too much from 50%, it may affect the performance of the circuit, and in the worst case, it may cause the circuit to malfunction. Therefore, in general, a circuit that can adjust the duty cycle of the frequency signal is required in the system. [0003] Generally speaking, the existing technology uses digital delay lines to adjust the duty cycle of frequency signals, such as "An all-digital 50% duty-cycle corrector, IEEE, 2004, page II-925-II-9...

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Problems solved by technology

[0003] Generally speaking, the existing technology uses digital delay lines to adjust the duty cycle of frequency signals, such as "An all-digital 50% duty-cycle corrector, IEEE, 2004, page II-925-II-928", however, digital The length of the delay line will be affected by the frequency of the frequency signal. When the frequency of the frequency signal is very low, a very long digital delay line will be required, resulting in an increase in chip area.

In addition, the design of the digital delay line itself also needs a longer length to reduce the quantization error of the above circuit

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