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Checking algorithm of NAND Flash memory chip

A verification algorithm and storage chip technology, applied in the field of multi-bit error checking and two-bit error correction verification algorithms for NAND Flash storage chips, can solve problems such as file system crashes, ensure integrity and accuracy, and reduce crashes the effect of risk

Inactive Publication Date: 2012-11-21
PAX COMP TECH SHENZHEN
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Problems solved by technology

[0007] 2. Flip caused by programming effect
The ECC verification algorithm can perform one-bit error correction and two-bit error detection for a page of NAND Flash. However, through high-stress tests, it is found that two-bit errors per page of NAND Flash sometimes occur. Once a two-bit error occurs , it will cause the file system built on NAND Flash to crash, so it is urgent to study a verification algorithm to reduce the risk of file system crash

Method used

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  • Checking algorithm of NAND Flash memory chip
  • Checking algorithm of NAND Flash memory chip
  • Checking algorithm of NAND Flash memory chip

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Embodiment Construction

[0051] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0052] see figure 1 , figure 2 with image 3 , the verification algorithm of the NAND Flash memory chip in the present embodiment, according to the row and column XOR value and the Hash value written in each page of data to the Spare area area, through the read data content of each page, the row and column XOR value in the Spare area area , the Hash value in the Spare area, the calculation results of the three can guarantee to correct one and two digit errors, and can find multi-bit errors, so as to ensure the integrity and accuracy of the data stored in the NAND Flash chip, and reduce Risk of ...

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Abstract

The invention is suitable for the checking algorithm field of NAND Flash memory chips, and provides a checking algorithm of an NAND Flash memory chip. Error data can be positioned and corrected through an operation result of read data contents of each page, a queue XOR value in a Spare area and a Hash value in the Spare area according to a queue XOR value of data of each page and a Hash value written into the Spare area to guarantee the correction of one-bit or two-bit errors and the discovery of multi-bit errors, so the integrity and the accuracy of the data stored in the NAND Flash memory chip are ensured, and the risk of file system crash is reduced.

Description

Technical field: [0001] The invention belongs to the field of verification algorithms for NAND Flash memory chips, and more specifically relates to a multi-bit error detection and two-bit error correction verification algorithm for NAND Flash memory chips. Background technique: [0002] Nowadays, NAND Flash memory chip is a common storage medium in the embedded field. Compared with NOR Flash memory chip, NAND Flash memory chip has the advantages of faster read and write speed and the ability to store more data. Therefore, NAND Flash memory chips have been widely favored by embedded device manufacturers. However, since NAND Flash memory chips cannot maintain the high reliability of stored data like NOR Flash memory chips, how to improve the reliability of data stored in NAND Flash memory chips? Reliability has become a difficult problem for all users. [0003] The basic composition of a NAND Flash chip is usually composed of multiple blocks, each block is composed of multipl...

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Application Information

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IPC IPC(8): G11C29/56
Inventor 万籁民韦献康刘绍海
Owner PAX COMP TECH SHENZHEN
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