Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor memory unit

A storage device and semiconductor technology, applied in information storage, static memory, digital memory information, etc., can solve the problems of difficult voltage level change speed, large load capacitance, power consumption, etc., reducing circuit area, reducing power consumption, The effect of shortening the readout time

Active Publication Date: 2012-12-19
SOCIONEXT INC
View PDF6 Cites 6 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, since the load capacitance of the wiring for supplying the write control signal is applied to the first and second local bit lines, it is difficult to increase the change speed of the voltage level of the first and second local bit lines.
Third, since the first and second global bit lines are connected to the gates of write transistors of a plurality of groups, the load capacitance of the first and second global bit lines is large
In this way, power is consumed due to useless charging and discharging and through current

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor memory unit
  • Semiconductor memory unit
  • Semiconductor memory unit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0035] figure 1 A configuration example of the semiconductor memory device according to Embodiment 1 is shown. The semiconductor storage device includes: a plurality of memory cells 101; a pair of local bit lines 104, 105; a pair of writing global bit lines 106, 107; a pair of reading global bit lines 108, 109; writing PMOS transistors TP0, TP1 ; write NMOS transistors TN0 , TN1 ; precharge PMOS transistors TPC0 , TPC1 (precharge circuit); write driver 110 ; read driver 111 ; A plurality of memory cells 101, a pair of local bit lines 104, 105, write PMOS transistors TP0, TP1, write NMOS transistors TN0, TN1, precharge PMOS transistors TPC0, TPC1, and readout circuits 112 are arranged in a plurality of blocks 102 , 103 in each. Precharge control signals PC, PC, write block selection signals PASS, PASS are given to blocks 102, 103, respectively. Furthermore, word line control signals WL, WL are given to the memory cells 101 included in the blocks 102, 103, respectively. In ...

Embodiment approach 2

[0073] figure 2 A configuration example of a semiconductor memory device according to Embodiment 2 is shown. The semiconductor memory device replaces figure 1 The illustrated readout circuit 112 includes a readout circuit 212 . Other composition and figure 1 The semiconductor memory devices shown are the same.

[0074] [Readout circuit]

[0075] The readout circuit 212 includes readout PMOS transistors TPR2, TPR3. The read PMOS transistor TPR2 has a source connected to the write global bit line 106 , a drain connected to the read global bit line 108 , and a gate connected to the local bit line 104 . The read PMOS transistor TPR3 has a source connected to the write global bit line 107 , a drain connected to the read global bit line 109 , and a gate connected to the local bit line 105 .

[0076] [action]

[0077] Next, explain figure 2 The operations of the semiconductor memory device (precharge operation, write operation, and read operation) are shown.

[0078] "Pr...

Embodiment approach 3

[0092] image 3 A configuration example of a semiconductor memory device according to Embodiment 3 is shown. The semiconductor memory device, replacing the figure 2 The shown precharge PMOS transistors TPC0 and TPC1 and the write driver 110 include a write driver 301 . Other composition and figure 2 The semiconductor memory devices shown are the same.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A transistor (TP0) comprises a source connected to a power source node, a drain connected to a local bit line (104), and a gate connected to a write global bit line (107). A transistor (TP1) comprises a source connected to a power source node, a drain connected to a local bit line (105), and a gate connected to a write global bit line (106). A transistor (TN0) comprises a source connected to the write global bit line (106), a drain connected to the local bit line (104), and a gate to which a control signal (PASS<0>) is provided. A transistor (TN1) comprises a source connected to the write global bit line (107), a drain connected to the local bit line (105), and a gate to which the control signal (PASS<0>) is provided. A readout circuit (112) is connected to the local bit lines (104, 105) and to readout global bit lines (108, 109).

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which bit lines are layered via transistors. Background technique [0002] In recent years, memories mounted on SOC (System On Chip) tend to increase in capacity and speed. With the increase in memory capacity, the number of memory cells connected to bit lines also increases. As a result, the load capacitance of the bit line increases, which hinders the increase in speed. Therefore, in order to reduce bit line capacitance, the following hierarchical bit line (hierarchical bit line) technology is known, that is, the bit line is divided into a plurality of banks (bank), and the memory cells in the bank are connected to the local bit line (local bit line). ) is connected, and the local bit line is connected to the global bit line (global bit line) via a transistor (for example, Patent Document 1). [0003] As in Patent Document 1 i...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/419G11C11/401G11C11/4096G11C11/41G11C11/417
CPCG11C11/413G11C7/18G11C7/12G11C2207/002
Inventor 小池刚中井洋次
Owner SOCIONEXT INC