Network communication cell used for multi-core microprocessor on-chip interconnected network

Abstract

The invention discloses a network communication cell used for a multi-core microprocessor on-chip interconnected network. The network communication cell used for the multi-core microprocessor on-chip interconnected network comprises at least a physic channel, wherein the physic channel comprises a communication interface unit and a two-stage pipeline structure; the communication interface unit comprises an interface register and not more than eight bidirectional communication interfaces; the two-stage pipeline structure comprises an arbitration station used for arbitrating an input message micro-packet data requirement and buffering input message micro-packet data, and a data selection station used for selectively outputting the arbitrated and allowed message micro-packet data; the arbitration station and the data selection station are respectively connected with the bidirectional communication interfaces through the interfere register; and an inter-station register used for caching the arbitrated and selected message micro-packet data is arranged between the arbitration station and the data selection station. The network communication cell used for the multi-core microprocessor on-chip interconnected network, disclosed by the invention, has the advantages of good reusability, simple configuration and extension, and capabilities of reducing design difficulty of the microprocessor interconnected network, shortening designing time and achieving a wide application range.

Description

Technical field [0001] The invention relates to a multi-core microprocessor-oriented on-chip interconnection network architecture, in particular to a network communication cell used for the multi-core microprocessor on-chip interconnection network. Background technique [0002] The basic forms of the on-chip interconnection network used in multi-core microprocessors are: bus, crossbar, ring, two-dimensional mesh (2D-mesh), two-dimensional ring network (2D-torus), and multi-dimensional mesh. [0003] The bus connects multiple processor cores (each core as a node) and provides time-sharing services to them through multiple interfaces. Only one source node can be connected to the destination node for each communication, and other nodes are disconnected. The bus is simple and practical, and the amount of equipment required is small. However, the number of nodes that can be connected and the operating frequency of the bus are related to the speed and drive capacity of the bus interface ...

AI Technical Summary

Problems solved by technology

[0009] In summary, there are the following problems in the design and implementation of the microprocessor on-chip interconnection network in the prior art: first, different application fields have different requirements for the number of cores integrated in the processor chip, so the on-chip interconnection network Second, the traditional multi-core processor on-chip network design is a custom design, which is realized through a dedicated circuit structure. Different processor manufacturers use dedicated on-chip interconnection networks when designing their own processor products. Circuit design, the design is difficult, the cycle is long, and the reusability is not strong

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