Equalizer circuit, data transmission system and equalization method

Abstract

The invention provides an equalizer circuit, a data transmission system and an equalization method. The equalizer circuit comprises a first adder, a decoder and a decision feedback equalizer, wherein the first adder receives a feedback signal and first input data which are output by a feed forward equalizer circuit, and is used for adding the first input data and the feedback signal to acquire an equalization output result; the decoder receives the equalization output result, and is used for decoding the equalization output result to acquire a decoding result; and the decision feedback equalizer receives the decoding result, and is used for filtering the decoding result on the basis of a first filter coefficient to acquire the feedback signal and outputs the feedback signal to the first adder, so that time-lag inter-symbol interference is eliminated. By the circuit, the system and the method, the decision feedback equalizer for filtering the output of a decision device to eliminate the inter-symbol interference is eliminated, so that error propagation can be avoided in the decision feedback equalizer.

Description

[0001] The invention relates to the communication field, in particular to an equalizing circuit, a data transmission system and an equalizing method. Background technique [0002] Gigabit Ethernet Physical Layer (GEPHY) is the electrical Ethernet physical layer. In the following, GEPHY specifically refers to the physical layer subsystem (module) implemented in the electrical port Ethernet communication chip, and the communication between the two parties is completed on the five or super five types of unshielded twisted pair (Unshielded Twisted Pair, UTP), and Need to support 1000BASE-T / 100BASE-TX / 10BASE-T protocol. In this article, especially the communication under the 1000BASE-T protocol standard is involved. [0003] According to the requirements of the IEEE specification, the 1000Base-T system transmits 4D-PAM5 signals at a modulation rate of 125MBaud on 4 pairs of unshielded twisted pairs, which can achieve 1Gb / s full-duplex data transmission. While the 4D-PAM5 signal i...

AI Technical Summary

Problems solved by technology

[0006] However, when the decision device makes a hard decision, if there is an error in the hard decision, the erroneous decision result dk output by the decision device will be kept in the delay register of the DFE for a period of time, so that during this period, the output of the DFE is inaccurate. That is, there is error propagation, which causes an error in the output signal rk of the equalizer

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