System for realizing digital-analog hybrid checking of filter

A digital-analog hybrid and filter technology, applied in the electronic field, can solve problems such as inability to converge, complex system-level verification, and long time, and achieve the effects of ensuring completeness, improving verification efficiency, and accelerating convergence

Inactive Publication Date: 2013-03-06
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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Problems solved by technology

[0007] In view of the problems existing in the above-mentioned prior art, the purpose of the present invention is to provide a verification method for realizing a digital-analog hybrid integrated circuit, sacrificing the accuracy of part of the analog signal simulation in exchange for faster system-level simulation. Faster simulation speed to solve the problems of complex system-level verification, long time and failure to converge in the existing technology

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  • System for realizing digital-analog hybrid checking of filter
  • System for realizing digital-analog hybrid checking of filter
  • System for realizing digital-analog hybrid checking of filter

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[0019] specific implementation plan

[0020] The core of the present invention is to use the real data (floating point data) of the verification language System Verilog to replace the analog signal, construct the analog component model, and realize the system level mixed signal verification of the Delat-Sigma filter. Compared with complete digital signal simulation, the invention has higher accuracy and faster system-level simulation speed. At the same time, verification methods such as System Verilog constrained random excitation, coverage statistics and assertion description can be applied.

[0021] The specific realization of the method of the present invention is as follows figure 1 As shown, specifically:

[0022] By verifying the floating-point data of the language System Verilog instead of analog or electrical simulation quantities, construct analog components digital-to-analog conversion module DA, channel selection module DeMux, de-channel signal selection module Mu...

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Abstract

The invention relates to a method for realizing digital-analog hybrid system stage checking of a Sigma-Delta filter. The core of the method is that real data (floating data) of a checking language System Verilog replaces an analog or electrical simulation variable, so that an analog component model and a checking environment are constructed, and hybrid signal checking of the Sigma-Delta filter is realized. The real data are continuously changed and are similar to an analog signal; the simulation time is a discrete variable; therefore, variable simulation based on the real data belongs to discrete event change; only a digital simulator is called to realize simulation of the real data; and the simulation speed is relatively high.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a method for realizing digital-analog hybrid integrated circuit verification. Background technique [0002] As mixed-signal SoC designs become increasingly complex, the need for integrated verification capabilities including analog, RF, and digital blocks increases. In order to realize system-level verification in a complete sense, it is necessary to use a combination of multiple simulators such as SPICE, RF simulator, and mixed-signal simulator. Each simulation verification method has its own advantages and disadvantages, examples are as follows. [0003] 1. Traditional transistor-level SPICE simulators have accurate simulation performance, but due to capacity and speed limitations, they are usually only suitable for block-level circuit design. [0004] 2. AMS provides a wider range of applications, and may have both fish and bear's paw. For experienced digital-analog hyb...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 杨晓坤
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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