System for realizing digital-analog hybrid checking of filter

Abstract

The invention relates to a method for realizing digital-analog hybrid system stage checking of a Sigma-Delta filter. The core of the method is that real data (floating data) of a checking language System Verilog replaces an analog or electrical simulation variable, so that an analog component model and a checking environment are constructed, and hybrid signal checking of the Sigma-Delta filter is realized. The real data are continuously changed and are similar to an analog signal; the simulation time is a discrete variable; therefore, variable simulation based on the real data belongs to discrete event change; only a digital simulator is called to realize simulation of the real data; and the simulation speed is relatively high.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a method for realizing digital-analog hybrid integrated circuit verification. Background technique [0002] As mixed-signal SoC designs become increasingly complex, the need for integrated verification capabilities including analog, RF, and digital blocks increases. In order to realize system-level verification in a complete sense, it is necessary to use a combination of multiple simulators such as SPICE, RF simulator, and mixed-signal simulator. Each simulation verification method has its own advantages and disadvantages, examples are as follows. [0003] 1. Traditional transistor-level SPICE simulators have accurate simulation performance, but due to capacity and speed limitations, they are usually only suitable for block-level circuit design. [0004] 2. AMS provides a wider range of applications, and may have both fish and bear's paw. For experienced digital-analog hyb...

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Problems solved by technology

[0007] In view of the problems existing in the above-mentioned prior art, the purpose of the present invention is to provide a verification method for realizing a digital-analog hybrid integrated circuit, sacrificing the accuracy of part of the analog signal simulation in exchange for faster system-level simulation. Faster simulation speed to solve the problems of complex system-level verification, long time and failure to converge in the existing technology

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