43 results about "Hybrid integrated circuit" patented technology

The invention relates to the technical field of analog and digital-analog hybrid integrated circuits, and discloses a bootstrap sampling switch circuit with a pre-charging function and an analog-to-digital converter. The circuit comprises a sampling switch module and a time sequence control module. The sampling switch module sequentially works at a holding phase, a pre-charging phase and a tracking phase under the control of a multi-phase clock signal generated by the time sequence control module, the pre-charging phase is added before the tracking phase, the grid voltage of a sampling switch is pre-boosted, and the pre-charging time is dynamically controlled by using an adjustable clock circuit, so that the pre-charging time of the sampling switch is dynamically controlled. Therefore, the charge sharing effect caused by the gate parasitic capacitance is effectively suppressed. The analog-to-digital converter comprises the sampling switch circuit. The linearity and the conduction characteristic of the sampling switch are remarkably improved, and the sampling switch has excellent time sequence configurability and is suitable for a high-speed and high-precision analog-to-digital conversion system.

The application discloses a preparation method of a self-selecting memory integrated with CMOS, and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. The application forms the electrical connection of a selector and a novel memory unit in a CMOS post-process, and constitutes a self-selecting memory structure. Compared with a traditional 1T1R structure, the application significantly improves the array density and reduces the process cost under the condition of meeting the same driving capacity.

The utility model relates to a lead bending tool for metal flat packaging of a hybrid integrated circuit. The lead bending tool comprises a clamping tool, an upper movable die is movably arranged below the clamping tool; a lower fixed mold is oppositely combined below the upper movable mold; the lower fixed mold and the upper movable mold are used for clamping an integrated circuit piece; a side insertion hole D is transversely formed in the upper movable mold; a bending bracket is inserted into the side insertion hole D; a pressing roller is arranged on the lower side of the bending bracket and is used for pressing the lead; a lengthened hollow column C is arranged on the upper top surface of the clamping tool; the device is reasonable in design, compact in structure and convenient to use.

The application relates to the technical field of integrated circuit hybrid integrated circuit packaging, in particular to a high-reliability high-density hybrid integrated packaging structure, which is composed of a ceramic base, a chip, a passive device, a metal ring frame and a cover plate, the ceramic base, the metal ring frame and the cover plate form an airtight cavity; the ceramic base is in a cubic structure, the front surface or the side surface except the bottom is used for mounting the chip or the passive device, the metal ring frame is arranged on the front surface or the side surface of the ceramic base to surround the chip or the passive device, and the cover plate is arranged on the metal ring frame to realize airtight packaging. The high-reliability high-density hybrid integrated packaging structure has the advantages of high performance, high reliability, high density, miniaturization, stable performance, long service life and the like.

The invention discloses a phase-locked loop integrated structure and a lock loss detection method thereof, and belongs to the field of digital-analog hybrid integrated circuits. In the structure, an on-chip clock outputs an IRC clock to a clock switching selection circuit; the phase-locked loop receives an external clock, carries out frequency division and frequency multiplication, outputs a PLL output clock to the clock switching selection circuit, and outputs a PLL locking instruction at the same time. The register configuration module writes input frequency division parameters, outputs frequency division parameters and frequency multiplication parameters and configures the parameters to the phase-locked loop, writes the upper limit and the lower limit of expected PLL output clock frequency and configures the upper limit and the lower limit to the PLL clock exception control module, and sets a register bit field; the PLL clock abnormity control module outputs a LOCK signal to the clock switching selection circuit, counts an IRC clock and a PLL output clock, and performs CPU reset or interruption through a register bit field; and the clock switching selection circuit selects the IRC clock or the PLL to output the clock to the CPU through the LOCK signal. According to the invention, the problem that the output clock frequency range cannot be accurately detected when the PLL loses lock in the prior art can be solved.

The invention discloses a low-power-consumption reference source, which belongs to the technical field of integrated circuit design and comprises a current biasing circuit and a reference voltage generating circuit. The current bias circuit isolates fluctuation change of the power supply voltage while reducing the power supply voltage through a depletion type transistor, and outputs bias current; according to the reference voltage generation circuit, a parallel enhanced transistor which works in a sub-threshold region and adopts a hybrid bias mode is used as a load, and a reference voltage which is subjected to temperature compensation, low in power consumption and not changed along with temperature fluctuation is obtained according to a bias current. Besides, the method can be realized only through ingenious planning of body end connection on a layout level, additional process steps and manufacturing cost are not increased, a flexible and effective compensation dimension is provided for a designer, accurate optimization can be carried out aiming at a specific process corner and a working temperature range, and the method is suitable for large-scale production. And the practicability and the reliability of the reference voltage source in various high-performance analog and digital-analog hybrid integrated circuits are greatly improved.

A small DC motor drive circuit module metal packaging method and packaging structure belong to the microelectronic packaging technical field. It includes metal tube seat, heat sink pit, cap ring, tube cap, tube seat pin, insulator, copper plated ceramic substrate, chip, bonding wire and packaging filling insulation glue. The heat sink pit is made in the inner cavity area of the metal tube seat, the cap ring is set on the top periphery of the metal tube seat, the tube seat pin is set through the bottom of the metal tube seat, the copper plated ceramic substrate is used as the circuit integrated board, the copper plated ceramic substrate is installed in the heat sink pit, the chip is attached and bonded, the packaging filling insulation glue is filled and solidified, and the metal tube cap is sealed and welded with the metal tube seat. It has the characteristics of small volume, high integrated power density and high integration. It solves the problems of large packaging volume, heavy weight and poor thermal reliability of the existing small DC motor drive circuit module. It is widely used in the technical field of semiconductor devices, semiconductor power devices and hybrid integrated circuit packaging.

The invention relates to the technical field of sensors, in particular to a high-density hybrid integrated circuit type digital pressure sensor which comprises a rigid circuit board directly welded to a pressure core, and the output end and the input end of the rigid circuit board are electrically connected with electrical connecting plates respectively. Flexible deformation plates are arranged between the rigid circuit board and the electrical connection plates at the two ends, and the flexible deformation plates are used for wrapping the electrical connection wires; the rigid circuit board and the electrical connection board are connected through the flexible deformation board in a wrapping manner, so that the situation that the sensor is damaged by stress can be reduced, and the mechanical adaptability in various fields is improved; the sensor can be integrated through the arranged HTCC high-temperature co-fired ceramic tube shell, traditional plastic packaging is abandoned, the size of the sensor can be reduced, the protection performance of the sensor can be improved, the vibration resistance and impact resistance of the sensor can be improved, and the use yield of the sensor can be guaranteed.

The invention belongs to the technical field of semiconductor hybrid integrated circuit design, and discloses a control circuit and method for a time sequence of a depletion type solid state power controller. Two ends of a first circuit structure in the control circuit are connected with power supply ends VDD and VEE to form a first path; one end of the second circuit structure is connected with the VDD, and the other end is connected with the GND end of the preceding-stage driving chip to form a second path; the in-phase end of the first comparator is connected with the first path, and the anti-phase end is connected with the second path. Two ends of the third circuit structure are connected with the VDD and the VEE to form a third path; the inverting end of the second comparator is connected with the output end of the first comparator through a third access, the in-phase end of the second comparator is connected with the MOSOUT end of the preceding-stage driving chip, and the output end of the second comparator is connected with the grid electrode of the depletion type VDMOS tube. According to the invention, the technical problem of transient power failure in the bias power-on and power-off processes of the depletion type intelligent power distribution safety switch is effectively solved.

The invention discloses a direct flight time information extraction method based on multistage quantization, and belongs to the technical field of digital-analog hybrid integrated circuits, and the method comprises the steps: detecting a flight time signal through SPAD; performing coarse and fine two-stage quantitative recording through a shift register and an analog counter; quantizing the analog level into a digital signal by adopting a multi-stage quantization circuit and generating a flight time histogram; a window signal is generated based on the coarse quantization time-of-flight histogram, and time amplification is realized through a time-to-analog conversion and amplification circuit; and finally, based on the coarse quantization time-of-flight histogram and the fine quantization time-of-flight histogram, extracting the time-of-flight and calculating the distance. According to the invention, the precision is ensured, and the memory resource demand and the system power consumption are obviously reduced.

A partially completed wafer contains complementary metal–oxide–semiconductor (CMOS) active devices formed with a CMOS fabrication line. Thin-film active devices are formed over the CMOS active devices with a thin-film fabrication line. Wiring between the CMOS active devices and the thin-film active devices may be formed with either or both fabrication lines. Wiring above the thin-film active devices may be formed with the thin-film fabrication line. The thin-film active devices and related wiring provide enhanced functionality to functionality provided by the CMOS active devices.

The application discloses a reading method of a novel memory and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. The novel memory is a nonvolatile memory, which comprises a CMOS transistor and a resistive random access memory (RRAM). The bottom electrode of the RRAM is connected with the drain end of the CMOS transistor. The RRAM is a four-terminal operating device. The reading operation of the novel memory specifically comprises the following steps: 1) performing the device electrical initialization (FORMING) and setting (SET) steps at the drain end (BL) of the transistor, and performing the resetting (RESET) operation at the source end (SL) of the transistor; and 2) controlling the gate of the transistor to apply an opening voltage, applying a reading voltage Vread at the SL end, and reading the current at the BL end. The application adopts the reading scheme in the same direction as the RESET, improves the current difference window on the premise of adopting a large reading voltage, and effectively suppresses the reading interference.

The application discloses a high-speed low-power comparator of a SAR ADC, and relates to the technical field of analog or digital-analog hybrid integrated circuits.The comparator comprises a pre-amplification stage and a latch stage, the enable signal cp end of the pre-amplification stage is connected with an enable signal Ki, the positive input end is connected with a differential input positive end signal vp, the negative input end is connected with a differential input negative end signal vn, the positive output end vop is connected with the positive input end of the latch stage through a switch K1, the negative output end von is connected with the positive input end of the latch stage through a switch K2, the switches K1 and K2 are controlled by the enable signal Ki, the differential input positive end signal vp is connected with the positive input end of the latch stage through a switch K3, the differential input negative end signal vn is connected with the positive input end of the latch stage through a switch K4, and the switches K3 and K4 are controlled by the inverted signal Kim of the enable signal Ki.The scheme improves the gain and bandwidth of the pre-amplification stage, thereby improving the speed and precision of the pre-amplification stage simultaneously.

The invention relates to a domestic autonomous controllable hybrid integrated circuit process design method based on product-level PDK modeling simulation. The method comprises the steps that process parameters of a hybrid integrated circuit product are designed, physical parameters of the hybrid integrated circuit product are extracted, a hybrid integrated circuit process design rule is established, and a PDK model framework is constructed. Using the neural network model to complete development of PDK components, and determining parameters of each component of the PDK model; designing a schematic diagram and a layout of the hybrid integrated circuit, importing the schematic diagram and the layout into a PDK model framework, and perfecting parameters of a PDK model; a complete hybrid integrated circuit product PDK model is built by using a domestic EDA tool, the model is in butt joint with the domestic EDA tool, and co-simulation and feedback optimization are performed on the PDK model. Through the PDK modeling simulation design, the problems that the process design period of hybrid integrated circuit products is long and the process design cannot fully meet the processing requirements are solved, the product design efficiency in the field is improved, and meanwhile, the electrical characteristics and the process reliability of the products are improved.

The invention relates to a packaging device and technology for a hybrid integrated circuit shell. The packaging device comprises a workbench, a conveying mechanism, a support, a pressing wheel, an arc-shaped plate, an abutting plate and a rotating plate. The device further comprises two sets of rotating discs distributed in a staggered mode, the edges of the rotating discs are fixedly connected with rotating rods rotationally connected in the abutting plate, the rotating rods are connected with the connecting pieces, the rotating discs are rotationally connected with limiting rings, and the limiting rings are fixedly connected with pressing plates penetrating out of the abutting plate. Through a transmission structure composed of the pressing wheel, the arc-shaped plate, the rotating plate, the rotating disc, the autorotation rod, the crimping plate, the meshing wheel and the like, a plurality of contact parts can be synchronously controlled to alternately or synchronously press the surface of a shell, and balance and uniformity of the stress direction of the shell are guaranteed; especially, due to the design that the two arc-shaped plates and the meshing wheels are matched with each other, the pressing wheels rotate in the opposite clock directions when working, the shell can be evenly clamped and cannot deflect in the sealing and pressing process, and the packaging quality is guaranteed.

The invention discloses glass powder and packaging slurry, and belongs to the technical field of packaging slurry, the glass powder comprises the following components by mass: 30-40 parts of silicon oxide, 5-10 parts of boric acid, 5-18 parts of a stability regulator, 2-10 parts of a softening point regulator, 3-10 parts of titanium oxide, and 1-5 parts of zirconium oxide; the softening point regulator comprises lithium carbonate and sodium carbonate in a mass ratio of (1-5): (1-5); the stability regulator comprises calcium carbonate and barium carbonate in a mass ratio of (2-8): (3-10). The photosensitive hyperfine high-temperature sintered glass powder with a high softening point is prepared, and the packaging slurry prepared from the glass powder can be used for preparing hyperfine glass patterns of 20 / 20 microns or above, so that the high-precision packaging requirement of a high-precision thick film hybrid integrated circuit is met; meanwhile, the influence of the glass powder on the resistance values of the silver wire and the resistor in the high-temperature sintering process is low; and 1.5%.

This invention discloses a low-power reference source, belonging to the field of integrated circuit design technology. The low-power reference source includes a current bias circuit and a reference voltage generation circuit. The current bias circuit reduces the power supply voltage while isolating voltage fluctuations through a depletion-type transistor, outputting a bias current. The reference voltage generation circuit uses parallel enhancement-mode transistors operating in the subthreshold region with a hybrid bias as a load to obtain a temperature-compensated, low-power reference voltage unaffected by temperature fluctuations based on the bias current. Furthermore, this invention can be implemented solely at the layout level through clever body-terminal interconnect planning, without adding additional process steps or manufacturing costs. It provides designers with a flexible and effective compensation dimension, enabling precise optimization for specific process corners and operating temperature ranges, greatly improving the practicality and reliability of the reference voltage source in various high-performance analog and mixed-signal integrated circuits.

The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-κ gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.

The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-κ gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.

The invention discloses a bonding method for enhancing gold wire bonding quality reliability, and belongs to the technical field of semiconductor thick film hybrid integrated circuit packaging. The bonding method comprises the following steps: (1) firstly, pre-planting gold balls on the thick film gold conduction band, and increasing the contact area and the bonding strength of a bonding point and the gold conduction band; and (2) carrying out safety ball bonding on the crescent, and tightly clamping the crescent between the two golden balls to form hamburger wrapping ball bonding. The problems that in an existing bonding technology, crescent bonding pseudo soldering exists, and the root of a bonding wire is prone to breakage are solved. The method is widely applied to the packaging technology of gold conduction band electronic components, in particular to the packaging technology of a semiconductor hybrid integrated circuit adopting a gold wire bonding structure.

The invention discloses a simulation optimization method and device for a zero crossing point event in an integrated circuit, and the method comprises the steps: receiving an input signal containing a Cross or Above event defined by a hardware description language, and storing the value of the input signal and a current moment; comparing the simulation point at the current moment with the simulation point at the previous moment, and predicting the next time point based on the simulation point data of the current moment and a plurality of historical zero-crossing points if the zero-crossing point is detected; and inserting a simulation calculation point on a simulation time axis according to the prediction time point. The method is used for simulation verification of analog and digital-analog hybrid integrated circuits, and particularly relates to performance optimization of a simulation tool on Cros / Alive events in a VerilogAMS hardware description language.

The application belongs to the technical field of hybrid integrated circuit electronic surface mounting, and particularly relates to a hybrid integrated circuit interconnection structure and a hybrid integrated circuit interconnection method. The hybrid integrated circuit interconnection structure comprises a structure body, a boss arranged above the structure body and forming a stepped structure with the structure body, and through holes penetrating through the structure body and the boss. The sidewall of the stepped structure is a rounded structure. The hybrid integrated circuit interconnection structure and the hybrid integrated circuit interconnection method can solve the problems in the prior art, improve the efficiency of structure preparation, reduce the material rejection rate of structure mounting, realize automatic mounting of the structure, and meet the demand of automatic production of hybrid integrated circuit products.

This invention discloses a high-precision multi-channel TDC circuit for lidar, relating to the field of mixed-signal integrated circuit technology. The circuit includes a delay phase-locked loop (10), an asynchronous counter (20), a phase detection circuit (30), a third-stage vernier measurement circuit (40), a decoding circuit (50), a data readout circuit (60), and a multi-event allocation circuit (70). This invention employs a three-stage cascaded quantization architecture, improving the delay phase-locked loop through a source-switched charge pump and operational amplifier negative feedback to suppress nonlinear distortion; eliminating misalignment errors by synchronizing the phase detection circuit with a three-stage D flip-flop; achieving ultra-high resolution of less than 50 ps through a vernier delay chain; and reducing measurement dead time through a multi-event allocation circuit. This invention can accurately quantize the time interval between lidar pulse transmission and reception, possessing a large dynamic range, high measurement accuracy, and multi-target adaptability, making it suitable for high-precision ranging scenarios in lidar.

The invention provides a product packaging structure with a metal shell and a preparation method thereof, and relates to the technical field of hybrid integrated circuit packaging. Wherein the heat dissipation tooth structure can improve the heat dissipation performance, and the purposes of weight reduction and light-weight design are achieved. The insulator structure arranged on the basis of the higher step area can improve the strength and reduce the defect rate. According to the magnetic device arranged in the middle sinking groove structure based on the heat-conducting pouring sealant and the heat-conducting insulating film, the heat-conducting and heat-dissipating requirements of the magnetic device are met, and the impact strength of the product is improved; and the signal control board is stacked on the magnetic device, so that the packaging density of the product is greatly improved. The fixed end structure greatly saves the installation and fixation space while improving the installation and fixation strength of the product, realizing the grounding of the shell and improving the electromagnetic shielding performance of the product. And the fixed end structure is connected with the substrate in a welding manner, so that a metal heat dissipation channel can be formed between the metal shell and the substrate, and the heat dissipation performance of the product is further improved.

The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to an assembly line ADC calibration method based on a graph convolutional neural network, which comprises the following steps: constructing an assembly line ADC error model comprising M cascaded sub-level modules, collecting analog voltage and inputting the analog voltage into the assembly line ADC error model, and obtaining code word data of each sub-level module to form a code word sequence; constructing a graph structure of an assembly line ADC error model, obtaining a normalized adjacent matrix, and constructing a node feature matrix according to the code word sequence; inputting the node feature matrix and the normalized adjacent matrix into a graph convolutional neural network to obtain a calibration coefficient of each sub-level module; each sub-level module and the calibration coefficient thereof are fused and then combined to form multi-level calibration output, and the multi-level calibration output and the weight matrix are combined to obtain a final calibration code word; according to the invention, the calibration precision is significantly improved.

The utility model belongs to the technical field of integrated circuit production, and particularly relates to a thick film hybrid integrated circuit drying device which comprises a thick film integrated circuit drying device, and a sealing plate is installed on the top of the thick film integrated circuit drying device. The top of the sealing plate is fixedly connected with a motor; the output end of the motor is fixedly connected with a guide rod; the bottom of the guide rod is fixedly connected with a fixed plate; a fixing unit is arranged in the fixing plate; a mounting plate is mounted at the bottom of the fixing plate through a fixing unit; then, the drying equipment is started for circumferential drying treatment, and in the drying process, a motor is started to drive a guide rod to rotate, so that the guide rod drives a fixing plate, a mounting plate, a supporting rod, a fixing ring, a connecting rod and the thick film hybrid integrated circuit mounting plate to rotate around the drying equipment; therefore, the thick film hybrid integrated circuit is uniformly dried, and the drying efficiency of the thick film hybrid integrated circuit is effectively improved.

The application belongs to the technical field of digital-analog hybrid integrated circuits, and relates to a high-precision low-latency exponential increment successive approximation analog-digital converter, which comprises an exponential delay integrator module, a multi-bit quantizer and a digital-analog converter module.The exponential delay integrator module is used for amplifying the residual voltage of the last round by using a proportional floating inverting amplifier, and is used for realizing exponential form integration and accumulation of the residual voltage by using a stacked capacitor module to control different stacked capacitors to work alternately in odd and even periods through ping-pong timing to delay and store the amplified residual voltage.The multi-bit quantizer is used for multi-bit quantization of the integrated signal to obtain a multi-bit digital signal.The digital-analog converter module is used for converting the multi-bit digital signal into an analog output signal to realize successive approximation logic.The exponential delay integrator module is realized by using a proportional floating inverting amplifier and a stacked capacitor module, which significantly reduces the circuit complexity and processing delay, and improves the robustness and energy efficiency of the system in high-precision application scenarios.

The invention provides a single-photon analog domain front-end circuit for an event-driven visual sensor, and relates to the technical field of digital-analog hybrid integrated circuits. The single-photon analog domain front-end circuit comprises an analog counting sub-circuit which is used for responding to reflected photons of a target scene in a preset time window, generating digital pulses and converting the digital pulses into a first voltage signal and a second voltage signal; the event-driven visual sensor unit is used for storing the first intensity value, subtracting the first intensity value from the second intensity value and outputting the intensity difference of adjacent frames; the high-low threshold comparator is used for comparing the intensity difference with a high threshold voltage and a low threshold voltage respectively to generate an event judgment signal; the output buffer is used for performing level shift processing on the event judgment signal and outputting an image; and the ADC unit is used for quantizing the second voltage signal into a digital signal. Therefore, on-chip resource consumption is low, the reading rate is high, and the defect that imaging is blurred when a high-speed moving object is recorded through traditional passive imaging is overcome.

1. The name of the design product: digital-analog hybrid high channel number test system case. 2. The use of the design product: for digital-analog hybrid integrated circuit test system, as the case of system power supply, channel board card and instrument plug-in. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view.

The application discloses a low-voltage and low-power asynchronous successive approximation analog-to-digital converter device, which comprises an asynchronous successive approximation analog-to-digital converter and an output buffer circuit, and the asynchronous successive approximation analog-to-digital converter is connected with the output buffer circuit, characterized in that the asynchronous successive approximation analog-to-digital converter comprises a sample-and-hold circuit, an N-bit capacitor array, an asynchronous dynamic comparator and asynchronous SAR logic; the sample-and-hold circuit is connected with the N-bit capacitor array and connected with the asynchronous dynamic comparator; and the asynchronous dynamic comparator is connected with the asynchronous SAR logic. The application is a kind of analog-to-digital converter with medium-low speed, medium-high precision and low power consumption. The application can be widely applied to the field of digital-analog hybrid integrated circuit design as a kind of low-voltage and low-power asynchronous successive approximation analog-to-digital converter device.