125 results about "Hybrid integrated circuit" patented technology

The invention discloses an in-memory computing array and an operation method thereof, and belongs to the technical field of semiconductors and CMOS hybrid integrated circuits. A 2T1R in-memory computing array based on subthreshold current is designed, each unit in the array is composed of a memristor, a gate tube T1 and a reading tube T2, write-in and erase operations are similar to a 1T1R array architecture, but read-out is carried out through the transistor T2 working in a subthreshold region, the reading current generated by the reading tube is small, and the read-in and erase operations can be carried out through the memristor, the gate tube T1 and the reading tube T2. And the parallelism degree of in-memory calculation is increased, and ultrahigh parallel calculation of 100-1000 orders of magnitude can be realized. And meanwhile, the reading current of the reading tube T2 is in exponential correlation with the gate voltage, so that a larger switching current ratio can be obtained, and a reading window of the in-memory calculation unit is amplified. Compared with a 1T1R array architecture, more complex in-memory calculation operation can be realized, and an operation strategy can be flexibly selected, so that more efficient multiply-accumulate operation is realized.

The invention relates to the technical field of digital-analog hybrid integrated circuit design, and particularly provides a FlexRay bus receiver with low noise and wide common-mode input range, which is characterized in that a common-mode voltage division module receives a differential signal output by a bus and carries out voltage division, and then a pre-amplification module carries out amplitude limiting amplification on the signal after voltage division; the hysteresis comparator module generates threshold hysteresis and generates a logic level signal based on the signal after amplitude limiting amplification, and the digital logic receiving module receives and processes the logic level signal, generates a receiving data signal and transmits the receiving data signal to an external controller. According to the invention, the differential signal pair received on the FlexRay bus is subjected to voltage division and amplitude limiting amplification, so that a wider common-mode input range is provided, the problem of large ground potential difference is solved, and the capability of suppressing common-mode noise and the communication stability are improved. Meanwhile, the hysteresis comparator module suppresses noise false triggering by generating threshold hysteresis, and the anti-noise capability of the receiver is remarkably improved.

The invention relates to the technical field of digital-analog hybrid integrated circuit design, and provides a resistance-capacitance hybrid analog-to-digital converter and a quantization method thereof. According to the resistance-capacitance hybrid analog-to-digital converter, a CDAC capacitor array is connected with the positive input end and the negative input end of a comparator, and the output end of the comparator is connected with an SAR control logic circuit; the reference voltage sampling capacitor unit is selectively connected between the output end of the RDAC resistor array and the ground to sample the output voltage of the RDAC resistor array, or is connected between the input end of the CDAC capacitor array and the output end of the RDAC resistor array to provide reference voltage for the CDAC capacitor array; in the sampling stage, the input voltage is stored on the CDAC, and meanwhile, the reference voltage sampling capacitor unit samples the output voltage of the RDAC; and in the conversion stage, the comparator obtains a comparison result according to the voltage at the output end of the CDAC, and controls the switching of the RDAC and the CDAC through the SAR control logic circuit according to the comparison result, thereby completing the successive approximation analog-to-digital conversion process.

The invention relates to the technical field of circuit data processing, and particularly discloses a high-integration hybrid integrated circuit thermal management method and system, and the method comprises the steps: obtaining integrated circuit structure data; performing data processing according to the integrated circuit structure to obtain a circuit structure heat dissipation demand index of each integrated area, and performing matching to obtain an initial heat dissipation strategy of each integrated area; according to working state data processing of the integrated circuit, working state heat dissipation demand indexes of all the integrated areas are obtained, and an initial heat dissipation strategy is triggered for heat dissipation; and performing comprehensive analysis to obtain a circuit heat dissipation effect evaluation value, and performing heat dissipation effect evaluation. According to the thermal management method and system for the high-integration hybrid integrated circuit, the potential heat dissipation problem can be found and solved in time, it is ensured that the circuit can stably operate under various working conditions, the optimal circuit layout, element packaging and heat dissipation strategies can be selected, and the service life of the circuit is prolonged. And furthermore, the product is ensured to have good heat dissipation performance in actual use, so that the product quality is improved.

The invention relates to the technical field of analog and digital-analog hybrid integrated circuits, and discloses a bootstrap sampling switch circuit with a pre-charging function and an analog-to-digital converter. The circuit comprises a sampling switch module and a time sequence control module. The sampling switch module sequentially works at a holding phase, a pre-charging phase and a tracking phase under the control of a multi-phase clock signal generated by the time sequence control module, the pre-charging phase is added before the tracking phase, the grid voltage of a sampling switch is pre-boosted, and the pre-charging time is dynamically controlled by using an adjustable clock circuit, so that the pre-charging time of the sampling switch is dynamically controlled. Therefore, the charge sharing effect caused by the gate parasitic capacitance is effectively suppressed. The analog-to-digital converter comprises the sampling switch circuit. The linearity and the conduction characteristic of the sampling switch are remarkably improved, and the sampling switch has excellent time sequence configurability and is suitable for a high-speed and high-precision analog-to-digital conversion system.

The invention relates to the technical field of circuit detection management, in particular to an intelligent detection method and system for a hybrid integrated circuit. The method comprises the following steps: installing an electrical parameter tester, an infrared thermal imager and an electromagnetic compatibility analyzer corresponding to different ports and key parts in the hybrid integrated circuit, and carrying out preparation before detection, so as to generate a test complete hybrid integrated circuit; starting synchronous acquisition according to a preset synchronous acquisition frequency to generate an electrical parameter set, chip working temperature distribution and a circuit operation electromagnetic radiation spectrum; performing fault detection according to the electrical parameter set, the chip working temperature distribution and the circuit operation electromagnetic radiation spectrum, and generating a corresponding fault detection result; and performing fault recommendation repair on the corresponding hybrid integrated circuit, and generating a fault degree recommendation repair scheme corresponding to the hybrid integrated circuit so as to execute corresponding hybrid integrated circuit fault repair work. According to the invention, the detection result can be accurately analyzed and fed back in real time.

The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to a high-precision low-power-consumption dynamic comparator circuit suitable for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-precision low-power-consumption dynamic comparator circuit is designed by adopting two-stage pre-amplification and a latch structure, a first-stage pre-amplification circuit A1 is a gain amplification stage, and a second-stage pre-amplification circuit A2 is a gain amplification stage; the effects of simplifying the circuit structure, reducing power consumption and eliminating kickback noise are achieved by adopting a dynamic operational amplifier of a cross-coupled load, the second-stage pre-amplification circuit A2 serves as an extra gain stage, an output signal from the first-stage pre-amplification circuit A1 can be quickly amplified by adopting a cross-coupled load structure, and the kickback noise is eliminated. The third-stage latch circuit A3 improves the speed of the comparator, the latch adopts a dynamic structure and is controlled by a dynamic clock, the latch does not work during resetting, and the static power consumption of the comparator is reduced.

The invention relates to a dynamic comparator offset voltage calibration method applied to SAR ADC upper pole plate sampling, and belongs to the field of digital-analog hybrid integrated circuit design. According to the method, the offset voltage of the comparator is calibrated by adjusting the switching voltage of a lower polar plate of a capacitor in the sampling stage of the successive approximation analog-to-digital converter; the quantization process of the digital-to-analog converter of the successive approximation analog-to-digital converter comprises a calibration mode and a normal working mode. In the calibration mode, common-mode voltage is sampled by using a successive approximation analog-to-digital converter and then quantized to obtain an offset code. And in a normal working mode, switching of a capacitor lower polar plate in the capacitor array is controlled according to the offset code during sampling, and then normal quantization is performed to obtain an output quantization code for eliminating the offset voltage of the comparator. According to the invention, a series of problems of narrowing of an input signal window caused by the offset voltage of the comparator can be eliminated, the logic is simple and easy to realize, the calibration precision is high, and real-time refreshing is not needed.

The invention provides a 1S1R storage unit and a preparation method thereof, and belongs to the technical field of semiconductors and CMOS hybrid integrated circuits. In the preparation process of the method, the preparation device comprising the first electrode layer, the gate layer and the buffer layer is subjected to annealing process treatment, so that the gate layer and the buffer layer are crystallized, after the gate layer is crystallized, the Forming voltage can be reduced, the threshold transformation characteristic yield of the device is improved, a protruding nanocrystalline interface is formed on the surface due to the crystallization of the buffer layer, and the yield of the device is improved. And meanwhile, local field intensity is also increased by a nanocrystalline interface, so that conductive filaments of the resistive layer are robust, the positions of the formed conductive filaments of the resistive layer have a certain rule, the randomness of the generation positions of the conductive filaments is reduced, and the uniformity of electrical properties is improved. The 1S1R unit structure is not only suitable for a 1S1R array of a Crossbar structure, but also suitable for a 1S1R array of a vertical structure after being properly modified, and has a wide application prospect.

The invention discloses a netlist extraction method for a digital-analog hybrid integrated circuit. The netlist extraction method comprises the following steps of: 1, finding a simulation library called by the digital-analog hybrid integrated circuit of which a netlist needs to be extracted; step 2, finding out each sub-module which directly calls the device in the simulation library; 3, deleting the sub-module netlists of all the sub-modules in the set A found in the step 2; 4, extracting a digital-analog hybrid integrated circuit netlist; 5, finding out pin description in the netlist of the digital-analog hybrid integrated circuit; 6, rewriting the internal netlist of each sub-module in the set A; and step 7, merging to obtain a complete digital-analog hybrid integrated circuit netlist. According to the method, a computer is used for directly extracting the bottom layer module netlist in the name mapping form, manual pin definition editing and checking modification are not needed any more, and the efficiency and accuracy of digital function simulation of the digital-analog hybrid integrated circuit are improved.

The application discloses a preparation method of a multifunctional self-selecting memristor based on a composite structure and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. The self-selecting memristor prepared by adopting the method has both volatile and nonvolatile resistive switching performances, and can realize the conversion from volatility to nonvolatility by changing electrical operation conditions. When the self-selecting memristor works in a volatile region, the self-selecting characteristic and short-range plasticity ability with high consistency are maintained; and when the self-selecting memristor works in a nonvolatile region, the self-selecting memristor has the advantages of low power consumption and a relatively large adjustable interval, and can maintain a storage state. The application has wide application potential in data storage and online learning scenes, and can realize efficient weight update and improve storage performance.

In an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.

An electronic assembly comprises: a carrier wafer having a wafer top surface and a wafer bottom surface; an electronic integrated circuit formed in the carrier wafer and including an integrated circuit contact pad on the wafer top surface; the carrier wafer comprising a through-wafer cavity having a wall, the wall connecting the wafer top surface to the wafer bottom surface; a component chip having a component chip top surface, a component chip bottom surface and a component chip side surface, the component chip being retained in the through-wafer cavity by direct contact of at least the side surface of the component chip with an attachment metal filling at least a portion of the through-wafer cavity; the component chip comprising at least one component contact pad on the component chip bottom surface; and a conductor connecting the integrated circuit contact pad and the component contact pad.

The application discloses a preparation method of a self-selecting memory integrated with CMOS, and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. The application forms the electrical connection of a selector and a novel memory unit in a CMOS post-process, and constitutes a self-selecting memory structure. Compared with a traditional 1T1R structure, the application significantly improves the array density and reduces the process cost under the condition of meeting the same driving capacity.

The utility model relates to a lead bending tool for metal flat packaging of a hybrid integrated circuit. The lead bending tool comprises a clamping tool, an upper movable die is movably arranged below the clamping tool; a lower fixed mold is oppositely combined below the upper movable mold; the lower fixed mold and the upper movable mold are used for clamping an integrated circuit piece; a side insertion hole D is transversely formed in the upper movable mold; a bending bracket is inserted into the side insertion hole D; a pressing roller is arranged on the lower side of the bending bracket and is used for pressing the lead; a lengthened hollow column C is arranged on the upper top surface of the clamping tool; the device is reasonable in design, compact in structure and convenient to use.

The present invention discloses an in-memory computing array and an operating method thereof, belonging to the field of semiconductor and CMOS hybrid integrated circuit technology. The present invention designs a 2T1R in-memory computing array based on subthreshold current. Each unit in the array consists of a memristor, a gate transistor T1, and a readout transistor T2. The write and erase operations are similar to those of a 1T1R array architecture, but the readout is performed through a transistor T2 operating in the subthreshold region. The readout current generated by the readout transistor is relatively small, which is conducive to increasing the parallelism of in-memory computing and can achieve ultra-high parallel computing of the order of 100 to 1000. At the same time, the readout current of the readout transistor T2 is exponentially related to the gate voltage, which can obtain a larger switching current ratio and amplify the readout window of the in-memory computing unit. Compared with the 1T1R array architecture, the present invention can realize more complex in-memory computing operations and can flexibly select operation strategies, thereby achieving more efficient multiplication and accumulation operations.

The utility model discloses a ceramic patch type packaging structure of a half-bridge driver, and belongs to the technical field of microelectronic device packaging. The structure comprises a ceramic base and a ceramic cover plate. The ceramic base is composed of a shell sealing ring, a ceramic base body, a heat sink area / chip assembly area and a back metal electrode. The back surface of the ceramic base body is provided with back metal electrodes which are arranged according to the requirements of a packaging circuit; the front surface of the ceramic base body is a circuit assembly frame body, the periphery of the frame body is a frame wall, the bottom surface of the frame body is a plane, the central area of the bottom surface of the frame body is a heat sink area / chip assembly area of a pit, a heat sink is assembled at the bottom of the pit, a chip is assembled on the surface of the heat sink, and the peripheral plane area of the pit is an internal metal conduction band and lead bonding area wiring layer. The problem that the existing all-silicon or all-GaN half-bridge driver packaging technology and packaging structure are difficult to meet the requirements of high heat dissipation, low input and output impedance, high insulativity and high reliability is solved. The method is widely applied to the technical field of product packaging of semiconductor power devices, hybrid integrated circuits and the like.

The application relates to the technical field of integrated circuit hybrid integrated circuit packaging, in particular to a high-reliability high-density hybrid integrated packaging structure, which is composed of a ceramic base, a chip, a passive device, a metal ring frame and a cover plate, the ceramic base, the metal ring frame and the cover plate form an airtight cavity; the ceramic base is in a cubic structure, the front surface or the side surface except the bottom is used for mounting the chip or the passive device, the metal ring frame is arranged on the front surface or the side surface of the ceramic base to surround the chip or the passive device, and the cover plate is arranged on the metal ring frame to realize airtight packaging. The high-reliability high-density hybrid integrated packaging structure has the advantages of high performance, high reliability, high density, miniaturization, stable performance, long service life and the like.

The invention discloses a phase-locked loop integrated structure and a lock loss detection method thereof, and belongs to the field of digital-analog hybrid integrated circuits. In the structure, an on-chip clock outputs an IRC clock to a clock switching selection circuit; the phase-locked loop receives an external clock, carries out frequency division and frequency multiplication, outputs a PLL output clock to the clock switching selection circuit, and outputs a PLL locking instruction at the same time. The register configuration module writes input frequency division parameters, outputs frequency division parameters and frequency multiplication parameters and configures the parameters to the phase-locked loop, writes the upper limit and the lower limit of expected PLL output clock frequency and configures the upper limit and the lower limit to the PLL clock exception control module, and sets a register bit field; the PLL clock abnormity control module outputs a LOCK signal to the clock switching selection circuit, counts an IRC clock and a PLL output clock, and performs CPU reset or interruption through a register bit field; and the clock switching selection circuit selects the IRC clock or the PLL to output the clock to the CPU through the LOCK signal. According to the invention, the problem that the output clock frequency range cannot be accurately detected when the PLL loses lock in the prior art can be solved.

The invention discloses a low-power-consumption reference source, which belongs to the technical field of integrated circuit design and comprises a current biasing circuit and a reference voltage generating circuit. The current bias circuit isolates fluctuation change of the power supply voltage while reducing the power supply voltage through a depletion type transistor, and outputs bias current; according to the reference voltage generation circuit, a parallel enhanced transistor which works in a sub-threshold region and adopts a hybrid bias mode is used as a load, and a reference voltage which is subjected to temperature compensation, low in power consumption and not changed along with temperature fluctuation is obtained according to a bias current. Besides, the method can be realized only through ingenious planning of body end connection on a layout level, additional process steps and manufacturing cost are not increased, a flexible and effective compensation dimension is provided for a designer, accurate optimization can be carried out aiming at a specific process corner and a working temperature range, and the method is suitable for large-scale production. And the practicability and the reliability of the reference voltage source in various high-performance analog and digital-analog hybrid integrated circuits are greatly improved.

A small DC motor drive circuit module metal packaging method and packaging structure belong to the microelectronic packaging technical field. It includes metal tube seat, heat sink pit, cap ring, tube cap, tube seat pin, insulator, copper plated ceramic substrate, chip, bonding wire and packaging filling insulation glue. The heat sink pit is made in the inner cavity area of the metal tube seat, the cap ring is set on the top periphery of the metal tube seat, the tube seat pin is set through the bottom of the metal tube seat, the copper plated ceramic substrate is used as the circuit integrated board, the copper plated ceramic substrate is installed in the heat sink pit, the chip is attached and bonded, the packaging filling insulation glue is filled and solidified, and the metal tube cap is sealed and welded with the metal tube seat. It has the characteristics of small volume, high integrated power density and high integration. It solves the problems of large packaging volume, heavy weight and poor thermal reliability of the existing small DC motor drive circuit module. It is widely used in the technical field of semiconductor devices, semiconductor power devices and hybrid integrated circuit packaging.

The invention discloses a screening system and method for hybrid integrated circuits. The system comprises an external power supply, test equipment, a screening circuit assembly and a test board, the test equipment is provided with a working condition tester and an interface box, the working condition tester is used for acquiring and processing working condition analog quantity data, the interface box is connected with an external power supply and a screening circuit assembly, and the test board is used for placing the screening circuit assembly; the screening circuit assembly is provided with a light source temperature control circuit, a screening light path, a test board, an SLD light source and a detector, the test board is provided with a test seat, the hybrid integrated circuit to be tested is installed on the test seat, the test board is further provided with a JTAG interface, and the screening light path is provided with an optical fiber ring. And during testing, whether the hybrid integrated circuit to be tested has communication abnormity and static test waveform abnormity is obtained by testing whether the RS422 serial port output on the test board is abnormal.

The invention relates to the technical field of sensors, in particular to a high-density hybrid integrated circuit type digital pressure sensor which comprises a rigid circuit board directly welded to a pressure core, and the output end and the input end of the rigid circuit board are electrically connected with electrical connecting plates respectively. Flexible deformation plates are arranged between the rigid circuit board and the electrical connection plates at the two ends, and the flexible deformation plates are used for wrapping the electrical connection wires; the rigid circuit board and the electrical connection board are connected through the flexible deformation board in a wrapping manner, so that the situation that the sensor is damaged by stress can be reduced, and the mechanical adaptability in various fields is improved; the sensor can be integrated through the arranged HTCC high-temperature co-fired ceramic tube shell, traditional plastic packaging is abandoned, the size of the sensor can be reduced, the protection performance of the sensor can be improved, the vibration resistance and impact resistance of the sensor can be improved, and the use yield of the sensor can be guaranteed.

The invention belongs to the technical field of semiconductor hybrid integrated circuit design, and discloses a control circuit and method for a time sequence of a depletion type solid state power controller. Two ends of a first circuit structure in the control circuit are connected with power supply ends VDD and VEE to form a first path; one end of the second circuit structure is connected with the VDD, and the other end is connected with the GND end of the preceding-stage driving chip to form a second path; the in-phase end of the first comparator is connected with the first path, and the anti-phase end is connected with the second path. Two ends of the third circuit structure are connected with the VDD and the VEE to form a third path; the inverting end of the second comparator is connected with the output end of the first comparator through a third access, the in-phase end of the second comparator is connected with the MOSOUT end of the preceding-stage driving chip, and the output end of the second comparator is connected with the grid electrode of the depletion type VDMOS tube. According to the invention, the technical problem of transient power failure in the bias power-on and power-off processes of the depletion type intelligent power distribution safety switch is effectively solved.

An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.

The embodiment of the utility model provides a square wave-sine wave conversion module, which relates to the technical field of circuit electronics, and specifically comprises a packaging shell, glass ceramics and a square wave-sine wave conversion circuit, and the glass ceramics and the square wave-sine wave conversion circuit are packaged and fixed in the packaging shell; the microcrystalline glass is fixed to the packaging shell through the adhesive film; the square wave-sine wave conversion circuit is fixed to the microcrystalline glass through a conductive adhesive; wherein the square wave-sine wave conversion circuit is integrated to the microcrystalline glass based on a thin film hybrid integrated circuit process. Therefore, the square wave-sine wave conversion circuit is integrally packaged through a thin film hybrid integrated circuit technology, and the square wave-sine wave conversion module with high integration level and miniaturization can be realized.

The present invention relates to a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit and a manufacturing method thereof, comprising sequentially forming a thin film resistor layer, a barrier layer and a thin gold seed crystal layer on the substrate; forming a gold conductive band on the thin gold seed crystal layer; removing the thin gold seed crystal layer; forming a nickel layer in the area to be nickel-plated; covering the pad gold layer on the nickel layer in the pad area; forming a thin film resistor network; and forming a nickel passivation layer. In the present invention, magnetron sputtering, photolithography technology, microelectronic electroplating process, degumming, corrosion technology and heat treatment process technology are used on an alumina ceramic substrate to form a gold conductive band and a nickel-chromium-silicon thin film resistor network respectively, and a nickel-gold burning solder pad and a solder resist layer are superimposed on the gold conductive band. The manufactured thin film substrate has a thick gold layer thickness, high line width accuracy and steep step morphology, which can meet the application requirements of high precision, high frequency and high reliability; the substrate structure is compatible with standard micro-assembly process and can be widely used in the field of thin film hybrid integrated circuits.

The invention provides a solid-state power relay based on a hybrid integrated circuit, which includes a boost circuit, a control circuit, a drive circuit, an optocoupler U1, a MOS transistor Q1, a buck circuit, a protection circuit, and an optocoupler U2. The input end of the control circuit is connected in parallel with the output end of the boost circuit and the output end of the optocoupler U1. The output end of the control circuit is connected in parallel with the input end of the protection circuit and the input end of the drive circuit. The output end of the drive circuit is connected to the gate of the MOS transistor Q1. The invention uses the method of boosting the voltage at the Vin terminal of the power supply to supply power to the control circuit and the drive circuit, and uses the method of bucking the voltage at the Vin terminal of the power supply to supply power to the protection circuit, so as to replace the power supply method of the isolation transformer and realize the on-off control function of the MOS transistor Q1. The boost circuit is used to detect the voltage value at the Vin terminal of the power supply to realize the overvoltage and undervoltage protection functions. Since the control signal requires a small current (≤5 mA), there is no need to install an isolation transformer, the circuit is simple, and the volume is small.

The utility model relates to the field of hybrid integrated circuits, in particular to a bonding tool for a hybrid integrated circuit, which comprises a substrate mounting device, a plurality of mounting grooves, a plurality of gas channels and vacuum holes, the mounting grooves are used for placing substrates and are arranged in an array, and the gas channels and the vacuum holes are communicated with one another. The plurality of gas channels comprise at least one first channel arranged along each column in the plurality of mounting grooves and at least one second channel arranged along each row, one end of the at least one gas channel penetrates through the main body and is used for being communicated with a negative pressure source, and the plurality of vacuum holes are used for being communicated with the bottoms of the plurality of mounting grooves and the gas channels; and negative pressure is formed between the mounting groove and the substrate to adsorb the substrate. According to the bonding tool provided by the invention, the damage to the substrate and the metal conduction band on the surface of the substrate can be reduced to the greatest extent while the substrate is ensured to be stably fixed in the mounting groove.

The invention relates to the technical field of digital-analog hybrid integrated circuit design, and particularly provides an anti-radiation low-jitter injection-locked phase-locked loop based on a threshold filtering technology, which comprises a pulse calibration circuit, a pulse injection unit and an injection-locked phase-locked loop, the pulse injection unit can generate an injection signal and a threshold signal according to a pulse calibration signal output by the pulse calibration circuit and a feedback signal output by the injection-locked phase-locked loop, so that whether the injection signal is output to the injection-locked phase-locked loop or not is judged according to the threshold signal. Reinforcement is performed based on an injection locked phase-locked loop structure, the pulse injection unit is provided, the threshold signal is generated while the injection signal is generated, and the conduction state of the injection path of the injection signal is controlled according to the threshold signal, so that the probability of wrong injection is greatly reduced, most injection errors are filtered from the source, and the injection accuracy is improved. Therefore, the jitter of the phase-locked loop is reduced, and the anti-radiation performance is improved.