92 results about "Hybrid integrated circuit" patented technology

The invention relates to the technical field of digital-analog hybrid integrated circuit design, and particularly provides a FlexRay bus receiver with low noise and wide common-mode input range, which is characterized in that a common-mode voltage division module receives a differential signal output by a bus and carries out voltage division, and then a pre-amplification module carries out amplitude limiting amplification on the signal after voltage division; the hysteresis comparator module generates threshold hysteresis and generates a logic level signal based on the signal after amplitude limiting amplification, and the digital logic receiving module receives and processes the logic level signal, generates a receiving data signal and transmits the receiving data signal to an external controller. According to the invention, the differential signal pair received on the FlexRay bus is subjected to voltage division and amplitude limiting amplification, so that a wider common-mode input range is provided, the problem of large ground potential difference is solved, and the capability of suppressing common-mode noise and the communication stability are improved. Meanwhile, the hysteresis comparator module suppresses noise false triggering by generating threshold hysteresis, and the anti-noise capability of the receiver is remarkably improved.

The invention relates to the technical field of analog and digital-analog hybrid integrated circuits, and discloses a bootstrap sampling switch circuit with a pre-charging function and an analog-to-digital converter. The circuit comprises a sampling switch module and a time sequence control module. The sampling switch module sequentially works at a holding phase, a pre-charging phase and a tracking phase under the control of a multi-phase clock signal generated by the time sequence control module, the pre-charging phase is added before the tracking phase, the grid voltage of a sampling switch is pre-boosted, and the pre-charging time is dynamically controlled by using an adjustable clock circuit, so that the pre-charging time of the sampling switch is dynamically controlled. Therefore, the charge sharing effect caused by the gate parasitic capacitance is effectively suppressed. The analog-to-digital converter comprises the sampling switch circuit. The linearity and the conduction characteristic of the sampling switch are remarkably improved, and the sampling switch has excellent time sequence configurability and is suitable for a high-speed and high-precision analog-to-digital conversion system.

The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to a high-precision low-power-consumption dynamic comparator circuit suitable for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-precision low-power-consumption dynamic comparator circuit is designed by adopting two-stage pre-amplification and a latch structure, a first-stage pre-amplification circuit A1 is a gain amplification stage, and a second-stage pre-amplification circuit A2 is a gain amplification stage; the effects of simplifying the circuit structure, reducing power consumption and eliminating kickback noise are achieved by adopting a dynamic operational amplifier of a cross-coupled load, the second-stage pre-amplification circuit A2 serves as an extra gain stage, an output signal from the first-stage pre-amplification circuit A1 can be quickly amplified by adopting a cross-coupled load structure, and the kickback noise is eliminated. The third-stage latch circuit A3 improves the speed of the comparator, the latch adopts a dynamic structure and is controlled by a dynamic clock, the latch does not work during resetting, and the static power consumption of the comparator is reduced.

The invention provides a 1S1R storage unit and a preparation method thereof, and belongs to the technical field of semiconductors and CMOS hybrid integrated circuits. In the preparation process of the method, the preparation device comprising the first electrode layer, the gate layer and the buffer layer is subjected to annealing process treatment, so that the gate layer and the buffer layer are crystallized, after the gate layer is crystallized, the Forming voltage can be reduced, the threshold transformation characteristic yield of the device is improved, a protruding nanocrystalline interface is formed on the surface due to the crystallization of the buffer layer, and the yield of the device is improved. And meanwhile, local field intensity is also increased by a nanocrystalline interface, so that conductive filaments of the resistive layer are robust, the positions of the formed conductive filaments of the resistive layer have a certain rule, the randomness of the generation positions of the conductive filaments is reduced, and the uniformity of electrical properties is improved. The 1S1R unit structure is not only suitable for a 1S1R array of a Crossbar structure, but also suitable for a 1S1R array of a vertical structure after being properly modified, and has a wide application prospect.

The application discloses a preparation method of a multifunctional self-selecting memristor based on a composite structure and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. The self-selecting memristor prepared by adopting the method has both volatile and nonvolatile resistive switching performances, and can realize the conversion from volatility to nonvolatility by changing electrical operation conditions. When the self-selecting memristor works in a volatile region, the self-selecting characteristic and short-range plasticity ability with high consistency are maintained; and when the self-selecting memristor works in a nonvolatile region, the self-selecting memristor has the advantages of low power consumption and a relatively large adjustable interval, and can maintain a storage state. The application has wide application potential in data storage and online learning scenes, and can realize efficient weight update and improve storage performance.

In an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.

The application discloses a preparation method of a self-selecting memory integrated with CMOS, and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. The application forms the electrical connection of a selector and a novel memory unit in a CMOS post-process, and constitutes a self-selecting memory structure. Compared with a traditional 1T1R structure, the application significantly improves the array density and reduces the process cost under the condition of meeting the same driving capacity.

The utility model relates to a lead bending tool for metal flat packaging of a hybrid integrated circuit. The lead bending tool comprises a clamping tool, an upper movable die is movably arranged below the clamping tool; a lower fixed mold is oppositely combined below the upper movable mold; the lower fixed mold and the upper movable mold are used for clamping an integrated circuit piece; a side insertion hole D is transversely formed in the upper movable mold; a bending bracket is inserted into the side insertion hole D; a pressing roller is arranged on the lower side of the bending bracket and is used for pressing the lead; a lengthened hollow column C is arranged on the upper top surface of the clamping tool; the device is reasonable in design, compact in structure and convenient to use.

The present invention discloses an in-memory computing array and an operating method thereof, belonging to the field of semiconductor and CMOS hybrid integrated circuit technology. The present invention designs a 2T1R in-memory computing array based on subthreshold current. Each unit in the array consists of a memristor, a gate transistor T1, and a readout transistor T2. The write and erase operations are similar to those of a 1T1R array architecture, but the readout is performed through a transistor T2 operating in the subthreshold region. The readout current generated by the readout transistor is relatively small, which is conducive to increasing the parallelism of in-memory computing and can achieve ultra-high parallel computing of the order of 100 to 1000. At the same time, the readout current of the readout transistor T2 is exponentially related to the gate voltage, which can obtain a larger switching current ratio and amplify the readout window of the in-memory computing unit. Compared with the 1T1R array architecture, the present invention can realize more complex in-memory computing operations and can flexibly select operation strategies, thereby achieving more efficient multiplication and accumulation operations.

The application relates to the technical field of integrated circuit hybrid integrated circuit packaging, in particular to a high-reliability high-density hybrid integrated packaging structure, which is composed of a ceramic base, a chip, a passive device, a metal ring frame and a cover plate, the ceramic base, the metal ring frame and the cover plate form an airtight cavity; the ceramic base is in a cubic structure, the front surface or the side surface except the bottom is used for mounting the chip or the passive device, the metal ring frame is arranged on the front surface or the side surface of the ceramic base to surround the chip or the passive device, and the cover plate is arranged on the metal ring frame to realize airtight packaging. The high-reliability high-density hybrid integrated packaging structure has the advantages of high performance, high reliability, high density, miniaturization, stable performance, long service life and the like.

The invention discloses a phase-locked loop integrated structure and a lock loss detection method thereof, and belongs to the field of digital-analog hybrid integrated circuits. In the structure, an on-chip clock outputs an IRC clock to a clock switching selection circuit; the phase-locked loop receives an external clock, carries out frequency division and frequency multiplication, outputs a PLL output clock to the clock switching selection circuit, and outputs a PLL locking instruction at the same time. The register configuration module writes input frequency division parameters, outputs frequency division parameters and frequency multiplication parameters and configures the parameters to the phase-locked loop, writes the upper limit and the lower limit of expected PLL output clock frequency and configures the upper limit and the lower limit to the PLL clock exception control module, and sets a register bit field; the PLL clock abnormity control module outputs a LOCK signal to the clock switching selection circuit, counts an IRC clock and a PLL output clock, and performs CPU reset or interruption through a register bit field; and the clock switching selection circuit selects the IRC clock or the PLL to output the clock to the CPU through the LOCK signal. According to the invention, the problem that the output clock frequency range cannot be accurately detected when the PLL loses lock in the prior art can be solved.

The invention discloses a low-power-consumption reference source, which belongs to the technical field of integrated circuit design and comprises a current biasing circuit and a reference voltage generating circuit. The current bias circuit isolates fluctuation change of the power supply voltage while reducing the power supply voltage through a depletion type transistor, and outputs bias current; according to the reference voltage generation circuit, a parallel enhanced transistor which works in a sub-threshold region and adopts a hybrid bias mode is used as a load, and a reference voltage which is subjected to temperature compensation, low in power consumption and not changed along with temperature fluctuation is obtained according to a bias current. Besides, the method can be realized only through ingenious planning of body end connection on a layout level, additional process steps and manufacturing cost are not increased, a flexible and effective compensation dimension is provided for a designer, accurate optimization can be carried out aiming at a specific process corner and a working temperature range, and the method is suitable for large-scale production. And the practicability and the reliability of the reference voltage source in various high-performance analog and digital-analog hybrid integrated circuits are greatly improved.

A small DC motor drive circuit module metal packaging method and packaging structure belong to the microelectronic packaging technical field. It includes metal tube seat, heat sink pit, cap ring, tube cap, tube seat pin, insulator, copper plated ceramic substrate, chip, bonding wire and packaging filling insulation glue. The heat sink pit is made in the inner cavity area of the metal tube seat, the cap ring is set on the top periphery of the metal tube seat, the tube seat pin is set through the bottom of the metal tube seat, the copper plated ceramic substrate is used as the circuit integrated board, the copper plated ceramic substrate is installed in the heat sink pit, the chip is attached and bonded, the packaging filling insulation glue is filled and solidified, and the metal tube cap is sealed and welded with the metal tube seat. It has the characteristics of small volume, high integrated power density and high integration. It solves the problems of large packaging volume, heavy weight and poor thermal reliability of the existing small DC motor drive circuit module. It is widely used in the technical field of semiconductor devices, semiconductor power devices and hybrid integrated circuit packaging.

The invention relates to the technical field of sensors, in particular to a high-density hybrid integrated circuit type digital pressure sensor which comprises a rigid circuit board directly welded to a pressure core, and the output end and the input end of the rigid circuit board are electrically connected with electrical connecting plates respectively. Flexible deformation plates are arranged between the rigid circuit board and the electrical connection plates at the two ends, and the flexible deformation plates are used for wrapping the electrical connection wires; the rigid circuit board and the electrical connection board are connected through the flexible deformation board in a wrapping manner, so that the situation that the sensor is damaged by stress can be reduced, and the mechanical adaptability in various fields is improved; the sensor can be integrated through the arranged HTCC high-temperature co-fired ceramic tube shell, traditional plastic packaging is abandoned, the size of the sensor can be reduced, the protection performance of the sensor can be improved, the vibration resistance and impact resistance of the sensor can be improved, and the use yield of the sensor can be guaranteed.

The invention belongs to the technical field of semiconductor hybrid integrated circuit design, and discloses a control circuit and method for a time sequence of a depletion type solid state power controller. Two ends of a first circuit structure in the control circuit are connected with power supply ends VDD and VEE to form a first path; one end of the second circuit structure is connected with the VDD, and the other end is connected with the GND end of the preceding-stage driving chip to form a second path; the in-phase end of the first comparator is connected with the first path, and the anti-phase end is connected with the second path. Two ends of the third circuit structure are connected with the VDD and the VEE to form a third path; the inverting end of the second comparator is connected with the output end of the first comparator through a third access, the in-phase end of the second comparator is connected with the MOSOUT end of the preceding-stage driving chip, and the output end of the second comparator is connected with the grid electrode of the depletion type VDMOS tube. According to the invention, the technical problem of transient power failure in the bias power-on and power-off processes of the depletion type intelligent power distribution safety switch is effectively solved.

The invention relates to the technical field of digital-analog hybrid integrated circuit design, and particularly provides an anti-radiation low-jitter injection-locked phase-locked loop based on a threshold filtering technology, which comprises a pulse calibration circuit, a pulse injection unit and an injection-locked phase-locked loop, the pulse injection unit can generate an injection signal and a threshold signal according to a pulse calibration signal output by the pulse calibration circuit and a feedback signal output by the injection-locked phase-locked loop, so that whether the injection signal is output to the injection-locked phase-locked loop or not is judged according to the threshold signal. Reinforcement is performed based on an injection locked phase-locked loop structure, the pulse injection unit is provided, the threshold signal is generated while the injection signal is generated, and the conduction state of the injection path of the injection signal is controlled according to the threshold signal, so that the probability of wrong injection is greatly reduced, most injection errors are filtered from the source, and the injection accuracy is improved. Therefore, the jitter of the phase-locked loop is reduced, and the anti-radiation performance is improved.

The invention relates to a calibration-free high-precision temperature sensor, which belongs to the technical field of digital-analog hybrid integrated circuits, and comprises a temperature current generation module which comprises an ICTAT current branch and an IPTAT current branch which are respectively used for generating current positively correlated with temperature and current negatively correlated with temperature; the integrating capacitor is connected with the ICTAT current branch and the IPTAT current branch through a charge pump switch; the first end of the comparator inputs integrating capacitor voltage, and the second end inputs reference voltage; the set end of the RS trigger is connected with the output end of the comparator, and a clock signal is accessed to the reset end of the RS trigger; the counter is connected with the Q end of the RS trigger and is used for carrying out downsampling counting on the output of the Q end of the RS trigger and outputting; wherein the charge pump switch is controlled according to the output of the Q end of the RS trigger; a base compensation resistor is arranged in an IPTAT current branch of the temperature current generation module and used for eliminating nonlinear errors caused by limited current gain of a bipolar transistor.

The utility model discloses a surface-mounted power hybrid integrated circuit module packaging structure, and belongs to the technical field of microelectronic device packaging. The packaging structure is packaged by adopting a ceramic shell and a metal assembly; a high-power chip and a low-power chip are integrated in different areas in a packaging cavity of a ceramic shell, the integration areas of the high-power chip and the low-power chip are in a step type, the low-power chip and the high-power chip are sequentially integrated from an upper step to a lower step, and seamless isolation and staggered-layer integration are carried out; the high-power chip is sintered on the heat sink, and the heat sink penetrates through the ceramic shell to realize internal and external electric connection; a TU1 material is used in a key parasitic parameter generation area of the packaging structure and penetrates through the ceramic cavity and the outside, and penetrating type connection is achieved. The surface-mounted high-power chip module packaging structure solves the problems of high parasitic impedance, low heat dissipation efficiency, low product power density, low integration level and large packaging size in the conventional surface-mounted high-power chip module packaging structure. The packaging structure is widely applied to the packaging technology of the power hybrid integrated circuit module.

The invention discloses a direct flight time information extraction method based on multistage quantization, and belongs to the technical field of digital-analog hybrid integrated circuits, and the method comprises the steps: detecting a flight time signal through SPAD; performing coarse and fine two-stage quantitative recording through a shift register and an analog counter; quantizing the analog level into a digital signal by adopting a multi-stage quantization circuit and generating a flight time histogram; a window signal is generated based on the coarse quantization time-of-flight histogram, and time amplification is realized through a time-to-analog conversion and amplification circuit; and finally, based on the coarse quantization time-of-flight histogram and the fine quantization time-of-flight histogram, extracting the time-of-flight and calculating the distance. According to the invention, the precision is ensured, and the memory resource demand and the system power consumption are obviously reduced.

A partially completed wafer contains complementary metal–oxide–semiconductor (CMOS) active devices formed with a CMOS fabrication line. Thin-film active devices are formed over the CMOS active devices with a thin-film fabrication line. Wiring between the CMOS active devices and the thin-film active devices may be formed with either or both fabrication lines. Wiring above the thin-film active devices may be formed with the thin-film fabrication line. The thin-film active devices and related wiring provide enhanced functionality to functionality provided by the CMOS active devices.

The application discloses a reading method of a novel memory and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. The novel memory is a nonvolatile memory, which comprises a CMOS transistor and a resistive random access memory (RRAM). The bottom electrode of the RRAM is connected with the drain end of the CMOS transistor. The RRAM is a four-terminal operating device. The reading operation of the novel memory specifically comprises the following steps: 1) performing the device electrical initialization (FORMING) and setting (SET) steps at the drain end (BL) of the transistor, and performing the resetting (RESET) operation at the source end (SL) of the transistor; and 2) controlling the gate of the transistor to apply an opening voltage, applying a reading voltage Vread at the SL end, and reading the current at the BL end. The application adopts the reading scheme in the same direction as the RESET, improves the current difference window on the premise of adopting a large reading voltage, and effectively suppresses the reading interference.

The application discloses a high-speed low-power comparator of a SAR ADC, and relates to the technical field of analog or digital-analog hybrid integrated circuits.The comparator comprises a pre-amplification stage and a latch stage, the enable signal cp end of the pre-amplification stage is connected with an enable signal Ki, the positive input end is connected with a differential input positive end signal vp, the negative input end is connected with a differential input negative end signal vn, the positive output end vop is connected with the positive input end of the latch stage through a switch K1, the negative output end von is connected with the positive input end of the latch stage through a switch K2, the switches K1 and K2 are controlled by the enable signal Ki, the differential input positive end signal vp is connected with the positive input end of the latch stage through a switch K3, the differential input negative end signal vn is connected with the positive input end of the latch stage through a switch K4, and the switches K3 and K4 are controlled by the inverted signal Kim of the enable signal Ki.The scheme improves the gain and bandwidth of the pre-amplification stage, thereby improving the speed and precision of the pre-amplification stage simultaneously.

The invention relates to a domestic autonomous controllable hybrid integrated circuit process design method based on product-level PDK modeling simulation. The method comprises the steps that process parameters of a hybrid integrated circuit product are designed, physical parameters of the hybrid integrated circuit product are extracted, a hybrid integrated circuit process design rule is established, and a PDK model framework is constructed. Using the neural network model to complete development of PDK components, and determining parameters of each component of the PDK model; designing a schematic diagram and a layout of the hybrid integrated circuit, importing the schematic diagram and the layout into a PDK model framework, and perfecting parameters of a PDK model; a complete hybrid integrated circuit product PDK model is built by using a domestic EDA tool, the model is in butt joint with the domestic EDA tool, and co-simulation and feedback optimization are performed on the PDK model. Through the PDK modeling simulation design, the problems that the process design period of hybrid integrated circuit products is long and the process design cannot fully meet the processing requirements are solved, the product design efficiency in the field is improved, and meanwhile, the electrical characteristics and the process reliability of the products are improved.

The invention relates to a packaging device and technology for a hybrid integrated circuit shell. The packaging device comprises a workbench, a conveying mechanism, a support, a pressing wheel, an arc-shaped plate, an abutting plate and a rotating plate. The device further comprises two sets of rotating discs distributed in a staggered mode, the edges of the rotating discs are fixedly connected with rotating rods rotationally connected in the abutting plate, the rotating rods are connected with the connecting pieces, the rotating discs are rotationally connected with limiting rings, and the limiting rings are fixedly connected with pressing plates penetrating out of the abutting plate. Through a transmission structure composed of the pressing wheel, the arc-shaped plate, the rotating plate, the rotating disc, the autorotation rod, the crimping plate, the meshing wheel and the like, a plurality of contact parts can be synchronously controlled to alternately or synchronously press the surface of a shell, and balance and uniformity of the stress direction of the shell are guaranteed; especially, due to the design that the two arc-shaped plates and the meshing wheels are matched with each other, the pressing wheels rotate in the opposite clock directions when working, the shell can be evenly clamped and cannot deflect in the sealing and pressing process, and the packaging quality is guaranteed.

The invention discloses glass powder and packaging slurry, and belongs to the technical field of packaging slurry, the glass powder comprises the following components by mass: 30-40 parts of silicon oxide, 5-10 parts of boric acid, 5-18 parts of a stability regulator, 2-10 parts of a softening point regulator, 3-10 parts of titanium oxide, and 1-5 parts of zirconium oxide; the softening point regulator comprises lithium carbonate and sodium carbonate in a mass ratio of (1-5): (1-5); the stability regulator comprises calcium carbonate and barium carbonate in a mass ratio of (2-8): (3-10). The photosensitive hyperfine high-temperature sintered glass powder with a high softening point is prepared, and the packaging slurry prepared from the glass powder can be used for preparing hyperfine glass patterns of 20 / 20 microns or above, so that the high-precision packaging requirement of a high-precision thick film hybrid integrated circuit is met; meanwhile, the influence of the glass powder on the resistance values of the silver wire and the resistor in the high-temperature sintering process is low; and 1.5%.

The application belongs to the technical field of digital-analog hybrid integrated circuit design, and specifically discloses a low-jitter sub-sampling phase-locked loop based on a discrete-time elimination technology, which comprises a sub-sampling phase-locked loop, a pulse generator and a discrete-time phase noise elimination path; wherein the discrete-time phase noise elimination path comprises a process, voltage and temperature tracking biasing device, a second sub-sampling phase detector, a direct current compensator and a level shifter; the application extracts output noise at the second sub-sampling phase detector and eliminates compensation before a ring oscillator, thereby significantly suppressing the phase noise of the sub-sampling phase-locked loop, and simultaneously adopting adaptive gain mismatch adjustment to ensure that the phase noise elimination maintains the best effect in process, voltage and temperature changes, compared with a traditional phase-locked loop based on a noise elimination module, the application eliminates the limitation on working frequency and power consumption, and avoids complex calibration.

This invention discloses a low-power reference source, belonging to the field of integrated circuit design technology. The low-power reference source includes a current bias circuit and a reference voltage generation circuit. The current bias circuit reduces the power supply voltage while isolating voltage fluctuations through a depletion-type transistor, outputting a bias current. The reference voltage generation circuit uses parallel enhancement-mode transistors operating in the subthreshold region with a hybrid bias as a load to obtain a temperature-compensated, low-power reference voltage unaffected by temperature fluctuations based on the bias current. Furthermore, this invention can be implemented solely at the layout level through clever body-terminal interconnect planning, without adding additional process steps or manufacturing costs. It provides designers with a flexible and effective compensation dimension, enabling precise optimization for specific process corners and operating temperature ranges, greatly improving the practicality and reliability of the reference voltage source in various high-performance analog and mixed-signal integrated circuits.

The invention discloses a large-scale array high-voltage high-precision differential output driving circuit, which relates to the field of digital-analog hybrid integrated circuits, realizes the conversion of K-bit digital signals of M * N channels, splits K-bit data into Q-bit and P-bit two-stage DACs (Digital-to-Analog Converters), and meanwhile, N groups of second-stage DACs share one first-stage DAC for output. The characteristic of high precision of a resistance DAC is reserved, the number of resistors needing to be matched is reduced, layout matching is ensured, meanwhile, the layout area is greatly reduced, the second-stage DAC achieves the level shift function through a proportional amplification circuit formed by a fully differential operational amplifier, and compared with a single-end operational amplifier, the second-stage DAC has the advantages that the first-stage DAC has the advantages of being simple in structure and convenient to use. The fully differential operational amplifier has high noise suppression capability and suppression capability on influence of offset error on output precision.

The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-κ gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.

The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-κ gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.