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Static image compression method based on two-dimensional discrete wavelet transform algorithm

A two-dimensional discrete wavelet, static image compression technology, applied in the direction of image communication, television, electrical components, etc., can solve the problem that it is difficult to meet the performance requirements of two-dimensional discrete wavelet transform, ASIC implementation is difficult to meet a variety of lengths, and the degree of algorithm flexibility Advanced problems, to solve the contradiction between algorithm performance and algorithm flexibility, improve overall performance, and achieve the effect of high efficiency

Inactive Publication Date: 2013-03-13
SOUTHEAST UNIV
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Problems solved by technology

The existing two-dimensional discrete wavelet transform algorithm has the characteristics of large amount of data calculation and high degree of algorithm flexibility. It is difficult for ASIC implementation to meet the requirements of the two-dimensional discrete wavelet transform algorithm with multiple lengths and multiple wavelet bases, and general calculation is difficult. Meet the performance requirements of two-dimensional discrete wavelet transform for massive data calculation

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  • Static image compression method based on two-dimensional discrete wavelet transform algorithm
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  • Static image compression method based on two-dimensional discrete wavelet transform algorithm

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Embodiment Construction

[0039] Below in conjunction with accompanying drawing and specific embodiment, further illustrate the present invention, should be understood that these embodiments are only for illustrating the present invention and are not intended to limit the scope of the present invention, after having read the present invention, those skilled in the art will understand various aspects of the present invention Modifications in equivalent forms all fall within the scope defined by the appended claims of this application.

[0040] Select the compression of a static image of QCIF (Quarter common intermediate format) resolution as an embodiment, after image preprocessing, adopt the lifting algorithm of two-dimensional 5 / 3 discrete wavelet transform to do discrete wavelet transform processing, adopt the present invention The system of the method described in the process of performing the 5 / 3 discrete wavelet transform is as follows figure 1 As shown, the process is the same as described in the...

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Abstract

The invention discloses a static image compression method based on a two-dimensional discrete wavelet transform algorithm. The static image compression method comprises the following steps of: pre-processing a source image; realizing the two-dimensional discrete wavelet transform algorithm on a reconfigurable architecture, and performing wavelet transform on the pro-processed image by virtue of the two-dimensional discrete wavelet transform algorithm which is realized on the reconfigurable architecture; and quantifying the image after the wavelet transform, then performing adaptive coding, passing through code-stream ordering, and finally forming the compressed image. According to the invention, contradiction between algorithm performance and algorithm flexibility is solved with the adoption of an innovative technology of the reconfigurable architecture; the algorithm is accelerated by the parallel computing capacity of the reconfigurable architecture on the premise of keeping the algorithm flexibility, so as to improve the algorithm performance; therefore, the overall performance of the image compression method is greatly improved, the efficiency is high, and the performance is better.

Description

technical field [0001] The invention belongs to the field of embedded information technology, specifically relates to a static image compression method based on a two-dimensional discrete wavelet transform algorithm, and more specifically relates to a static image compression method based on a reconfigurable technology to realize a two-dimensional discrete wavelet transform algorithm. It is applied to the core part of image processing in the design of high-performance embedded reconfigurable architecture system-on-chip for image processing. Background technique [0002] In the computing model that the public has become accustomed to, processors and application-specific integrated circuits (ASICs) have always been the two mainstreams. With the continuous improvement of application fields, especially embedded environments, for system performance, energy consumption, time-to-market and other indicators, traditional computing models have exposed various drawbacks. [0003] The ...

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Application Information

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IPC IPC(8): H04N7/26H04N19/436H04N19/63
Inventor 曹鹏柯鑫翔齐志杨锦江杨军时龙兴
Owner SOUTHEAST UNIV
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