Nonvolatile memory IP core test and verify exploitation system

Abstract

The invention discloses a nonvolatile memory IP core test and verify exploitation system, which comprises a power supply module used for providing power supply for each module in the system; a NVM IP core which is an object to be tested, to be exploited and to be verified; a BIST circuit which is connected to the NVM IP core and is used for testing the NVM IP; a host computer which has test software used for controlling the BIST circuit to operate various tests; a FPGA which is connected to the NVM IP core and is used for exploiting the NVM IP core; a FPGA configuration circuit which is connected to a FPGA chip and is used for downloading and writing of a FPGA digital logic; and a FPGA peripheral circuit which is used for connecting to the FPGA chip and is used for displaying and debugging. The nonvolatile memory IP core test and verify exploitation system integrates test, exploitation and verification as one body, the NVM IP core exploitation, exploitation and verification by the client is substantially accelerated, and the time and the cost of NVM IP core client flow sheet can be saved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to the testing technology, development technology and verification technology of non-volatile memory (NVM, Non-Volatile Memory). Background technique [0002] IP core (IP core, Intellectual Property core, intellectual property core) is those IC (integrated circuit) modules that have been verified, can be reused, and have certain functions. Divided into soft IP core, solid IP core and hard IP core. [0003] The soft IP core (soft IP core) is a functional block described in a hardware description language (HDL, Hardware Description Language), but does not involve any specific circuits and circuit elements to realize these functions. Soft IP cores usually appear in the form of hardware description language source files. [0004] In addition to completing all the design of the soft IP core, the firm IP core also completes the design links such as gate-leve...

AI Technical Summary

Problems solved by technology

Therefore, this environment can only verify the digital logic other than the NVM IP core interface logic, and cannot provide verification of the correctness of the NVM IP core operation

[0009] 2. There is no dedicated test environment for NVM IP cores. Since there is no dedicated NVM IP core, the environment used, such as specific power supply voltage conditions and specific connection characteristics, are all for general-purpose FLASH chips, and cannot be used for NVM IP cores. Performance testing, such as simulation parameter test, read and write mode test, read and write life test, read and write speed test, etc.

[0010] 3. Due to the inability to provide a dedicated test environment for NVM IP cores, the FLASH chip used for verification is inconsistent with the actual NVM IP core interfaces, functions, and simulation performance parameters. Such a verification environment can only partially verify logic functions and cannot guarantee verification. completeness and correctness

Images