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a memory architecture

A memory and memory bar technology, applied in the protection of internal/peripheral computer components, generation of response errors, error detection of redundant codes, etc., can solve the problem of write loss, slow read and write speed of phase change memory and STT-RAM and other issues to achieve the effect of low write loss, fast read and write speed, and strong data security

Active Publication Date: 2015-12-02
TSINGHUA UNIV
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Problems solved by technology

However, various technologies have different disadvantages in terms of ECC support, arbitrary proxy, fault tolerance, secure access, and memory encryption. For example, phase change memory and STT-RAM have slow read and write speeds and write loss

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Embodiment Construction

[0024] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0025] A memory architecture according to an embodiment of the present invention, the multifunctional memory architecture is composed of a memory stick and a memory controller, the memory stick is composed of storage devices, and the memory controller supports multiple storage devices and multiple functions.

[0026] The storage devices are heterogeneous or homogeneous storage devices, and the structures of the storage devices are non-hierarchical or hierarchical. The memory device includes a nonvolatile memory device chip and a volatile memory device chip.

[0027] The number of memory chips of the storage device is greater than the number of memory chips of the non-ECC ...

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Abstract

The invention discloses memory architecture. The memory architecture consists of a memory bank and a memory controller, wherein the memory bank consists of a volatile memory device and a nonvolatile memory device; and the memory controller supports simultaneous work of a plurality of storage devices, and supports an ECC (Error Correction Code) function, an any agent function, a fault-tolerance function, an enhanced safety access function and a memory encryption function. Due to the adoption of the memory architecture disclosed by the invention, a parallel hybrid structure of a heterogeneous storage chip is realized, a plurality of functions are supported, the system data writing loss is small, and the safe safety is high.

Description

technical field [0001] The invention relates to the field of computer structures, in particular to a memory architecture. Background technique [0002] The rate at which computer memory improves performance lags far behind the rate at which processor performance increases. Compared with the processor, the memory access delay increases at a rate of 5 times every ten years. The imbalance of this system structure forms a "storage wall" that hinders the performance improvement of the processor, thus making the memory system become the performance of the entire computer system. One of the bottlenecks. In order to solve this problem, many new memory technologies have been proposed. Such as DRAM, phase change memory, STT-RAM, etc. However, various technologies have different disadvantages in terms of ECC support, arbitrary proxy, fault tolerance, secure access, and memory encryption. For example, phase change memory and STT-RAM have slow read and write speeds and write loss. C...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F21/79G06F11/08
Inventor 汪东升高鹏王海霞
Owner TSINGHUA UNIV
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