Flat multichip packaging piece with stamping frame with square groove and production method of flat multichip packaging piece

Abstract

The invention discloses a flat multichip packaging piece with a stamping frame with a square groove and a production method of the flat multichip packaging piece. The packaging piece mainly comprises a lead frame, the square groove, a lower chip, an upper chip, a lower surface mount adhesive, an upper surface mount adhesive, a lower bonding wire, a middle bonding wire, an upper bonding wire and a plastic package body, the square groove is reserved on the lead frame which is adhered with the lower chip through the lower surface mount adhesive, the lower chip is adhered with the upper chip via the upper surface mount adhesive, the lower bonding wire is connected with the lead frame and the lower chip, the middle bonding frame is connected with the upper surface mount adhesive and the upper surface mount adhesive, the upper bonding wire is connected with the upper surface mount adhesive and the lead frame, the plastic package body surrounds the lead frame, the lower chip, the upper chip, the lower surface mount adhesive, the upper surface mount adhesive, the lower bonding wire, the middle bonding wire and the upper bonding wire and particularly fills the square groove, and the lead frame, the lower chip, the upper chip, the lower bonding wire, the middle bonding wire and the upper bonding wire form a power source and a signal channel of a circuit. The plastic package body is combined with the lead frame more firmly, and delamination-resisting effect is better.

Description

[0001] technical field [0002] The invention belongs to the technical field of integrated circuit packaging, in particular to a flat multi-chip package with a stamping frame with square grooves and a manufacturing method thereof. Background technique [0003] QFN (four-sided flat no-lead package) and DFN (dual flat no-lead package) packages have been developed in recent years with the emergence of communication and portable small digital electronic products (digital cameras, mobile phones, PCs, MP3) , Applicable to the packaging of small and medium-sized integrated circuits with high frequency, broadband, low noise, high thermal conductivity, small volume, high speed and other electrical requirements. We know that the QFN / DFN package effectively utilizes the package space of the lead pins, thereby greatly improving the package efficiency. However, at present, most semiconductor packaging manufacturers face some difficulties in the selection of frames in the manufacturing p...

AI Technical Summary

Problems solved by technology

[0005]1. The combination of integrated circuit chip and carrier is not good. When affected by changes in the external environment, it will cause layered defects inside the product, resulting in performance degradation , or even fail;

[0006]2. The bonding force between the back of the carrier and the plastic encapsulant is not good. When affected by the external environment, it will cause product defects (delamination); or the exposed carrier (base island) with thicker flash

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