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A self-testing method for a multi-node system on a chip of a large-scale microsystem chip

A multi-node, self-testing technology, applied in transmission systems, digital transmission systems, electrical components, etc.

Active Publication Date: 2015-08-12
无锡美森微电子科技有限公司
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

Therefore, how to control the test process of the interconnection line and count its test information and judge whether the test is over is a key issue, but there is no such technology at present

Method used

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  • A self-testing method for a multi-node system on a chip of a large-scale microsystem chip
  • A self-testing method for a multi-node system on a chip of a large-scale microsystem chip
  • A self-testing method for a multi-node system on a chip of a large-scale microsystem chip

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Embodiment Construction

[0066] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0067] According to an embodiment of the present invention, such as Figure 1-Figure 4As shown, a self-test method of a multi-node system on a chip of a large-scale microsystem chip is provided, which belongs to a test method of a large-scale microsystem chip (System-on-Chip, SoC), specifically a A built-in self-test (Build-In Self Test, BIST) method for the interconnection lines between the routers (Routers) in the SoC using the Network-on-Chip (NoC) as the interconnection structure. It can be used for the built-in self-test technology of the interconnection lines between the routers in the microsystem chip that uses the network on chip as the interconnection struc...

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Abstract

The invention discloses a self-testing method for an on-chip multi-node system for a large-scale micro-system chip. The method mainly comprises steps that initialized setting is performed on a router in the multi-node system, a test source is set, the test source can start a parallel self-testing procedure of the router when the on-chip multi-node system is started, and static test information of the parallel self-testing procedure is calculated. The self-testing method for the on-chip multi-node system for the large-scale micro-system chip can overcome the shortcomings that interconnection lines between the routers in the multi-node system on the large-scale micro-system chip cannot be tested and the like in the prior art, and achieves the advantages of accurate test results and less total test time.

Description

technical field [0001] The invention relates to the field of chip testing, in particular to a self-testing method of an on-chip multi-node system of a large-scale microsystem chip. Background technique [0002] Due to its good scalability and advantages in chip performance, hardware overhead and power consumption, the Network-on-Chip (NoC) interconnect structure is gradually becoming a large-scale microsystem chip (System-on-Chip, SoC) design trends. [0003] NoC can be divided into two types according to the topological regularity: 1. Homogeneous interconnection network, that is, a rule architecture applicable to the interconnection of the same IP core, such as Mesh architecture, fat trees architecture, etc.; 2. Heterogeneous interconnection network, that is, applicable Due to the irregular architecture of interconnection of different IP cores, such as the interconnection architecture integrating different IP cores such as CPU, DSP, RAM, and Co-process. However, the wides...

Claims

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Application Information

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IPC IPC(8): H04L12/26
Inventor 惠志达阿克塞尔·詹奇鲁中海朱红雷
Owner 无锡美森微电子科技有限公司
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